A survey on application map** strategies for network-on-chip design
Application map** is one of the most important dimensions in Network-on-Chip (NoC)
research. It maps the cores of the application to the routers of the NoC topology, affecting the …
research. It maps the cores of the application to the routers of the NoC topology, affecting the …
[書籍][B] Network-on-chip: the next generation of system-on-chip integration
S Kundu, S Chattopadhyay - 2014 - library.oapen.org
Addresses the Challenges Associated with System-on-Chip Integration Network-on-Chip:
The Next Generation of System-on-Chip Integration examines the current issues restricting …
The Next Generation of System-on-Chip Integration examines the current issues restricting …
Design and analysis of application specific network on chip for reliable custom topology
Abstract Network on Chip (NoC) is a communication sub-system formed among the
Intellectual Property (IP) cores in System on Chip (SoC). Routers, Links and network …
Intellectual Property (IP) cores in System on Chip (SoC). Routers, Links and network …
Power-aware map** for 3D-NoC designs using genetic algorithms
Abstract Scalable 3D Networks-on-Chip (NoC) designs are needed to match the ever-
increasing communication and low-power demands of large-scale multi-core applications …
increasing communication and low-power demands of large-scale multi-core applications …
A reliability-aware design methodology for networks-on-chip applications
Network reliability is a key design issue that impacts the performance of all Networks-on-
Chip-based systems. In this paper, we develop two reliability models for on-chip …
Chip-based systems. In this paper, we develop two reliability models for on-chip …
Power consumption of 3D networks-on-chips: Modeling and optimization
Designing power-efficient Networks-on-Chips (NoCs) for 3D ICs has emerged as a
promising solution for complex mobile and portable applications. The total power …
promising solution for complex mobile and portable applications. The total power …
A delay-aware topology-based design for networks-on-chip applications
H Elmiligi, AA Morgan… - 2009 4th International …, 2009 - ieeexplore.ieee.org
Network delay is a major design parameter for Networks-on-Chip (NoC)-based applications.
Improving NoC delay could be achieved at different design phases. At the system level, we …
Improving NoC delay could be achieved at different design phases. At the system level, we …
More is less, less is more: Molecular-scale photonic noc power topologies
Molecular-scale Network-on-Chip (mNoC) crossbars use quantum dot LEDs as an on-chip
light source, and chromophores to provide optical signal filtering for receivers. An mNoC …
light source, and chromophores to provide optical signal filtering for receivers. An mNoC …
Area-aware topology generation for Application-Specific Networks-on-Chip using network partitioning
AA Morgan, H Elmiligi… - 2009 IEEE Pacific …, 2009 - ieeexplore.ieee.org
One of the challenging problems in application-specific networks-on-chip (ASNoC) design is
customizing the topological structure of the on-chip network in order to meet the application …
customizing the topological structure of the on-chip network in order to meet the application …
Application-specific networks-on-chip topology customization using network partitioning
One of the most challenging problems in Application-Specific Networks-on-Chip (ASNoC)
design is to customize the topological structure of the on-chip network in order to meet the …
design is to customize the topological structure of the on-chip network in order to meet the …