Hardware-assisted machine learning in resource-constrained IoT environments for security: review and future prospective

G Kornaros - IEEE Access, 2022 - ieeexplore.ieee.org
As the Internet of Things (IoT) technology advances, billions of multidisciplinary smart
devices act in concert, rarely requiring human intervention, posing significant challenges in …

A survey on risc-v-based machine learning ecosystem

S Kalapothas, M Galetakis, G Flamis, F Plessas… - Information, 2023 - mdpi.com
In recent years, the advancements in specialized hardware architectures have supported the
industry and the research community to address the computation power needed for more …

Towards develo** high performance RISC-V processors using agile methodology

Y Xu, Z Yu, D Tang, G Chen, L Chen… - 2022 55th IEEE/ACM …, 2022 - ieeexplore.ieee.org
While research has shown that the agile chip design methodology is promising to sustain
the scaling of computing performance in a more efficient way, it is still of limited usage in …

Cfu playground: Full-stack open-source framework for tiny machine learning (tinyml) acceleration on fpgas

S Prakash, T Callahan, J Bushagour… - … Analysis of Systems …, 2023 - ieeexplore.ieee.org
Need for the efficient processing of neural networks has given rise to the development of
hardware accelerators. The increased adoption of specialized hardware has highlighted the …

Aurora: Virtualized accelerator orchestration for multi-tenant workloads

S Kim, J Zhao, K Asanovic, B Nikolic… - Proceedings of the 56th …, 2023 - dl.acm.org
With the widespread adoption of deep neural networks (DNNs) across applications, there is
a growing demand for DNN deployment solutions that can seamlessly support multi-tenant …

Shef: Shielded enclaves for cloud fpgas

M Zhao, M Gao, C Kozyrakis - Proceedings of the 27th ACM International …, 2022 - dl.acm.org
FPGAs are now used in public clouds to accelerate a wide range of applications, including
many that operate on sensitive data such as financial and medical records. We present …

X-heep: An open-source, configurable and extendible risc-v microcontroller for the exploration of ultra-low-power edge accelerators

S Machetti, PD Schiavone, TC Müller… - arxiv preprint arxiv …, 2024 - arxiv.org
The field of edge computing has witnessed remarkable growth owing to the increasing
demand for real-time processing of data in applications. However, challenges persist due to …

CEDR: A compiler-integrated, extensible DSSoC runtime

J Mack, S Hassan, N Kumbhare… - ACM Transactions on …, 2023 - dl.acm.org
In this work, we present a C ompiler-integrated, E xtensible D omain Specific System on
Chip R untime (CEDR) ecosystem to facilitate research toward addressing the challenges of …

An eight-core RISC-V processor with compute near last level cache in Intel 4 CMOS

GK Chen, PC Knag, C Tokunaga… - IEEE Journal of Solid …, 2022 - ieeexplore.ieee.org
An eight-core 64-b processor extends RISC-V to perform multiply–accumulate (MAC) within
the shared last level cache (LLC). Instead of moving data from the LLC to the core, compute …

Domain-specific architectures: Research problems and promising approaches

A Krishnakumar, U Ogras, R Marculescu… - ACM Transactions on …, 2023 - dl.acm.org
Process technology-driven performance and energy efficiency improvements have slowed
down as we approach physical design limits. General-purpose manycore architectures …