Fault testing for reversible circuits

KN Patel, JP Hayes, IL Markov - IEEE Transactions on …, 2004 - ieeexplore.ieee.org
Applications of reversible circuits can be found in the fields of low-power computation,
cryptography, communications, digital signal processing, and the emerging field of quantum …

ORGAN DONATION: KEY FACTORS INFLUENCING FAMILIES'DECISION-MAKING

M Sque, T Long, S Payne - Transplantation, 2004 - journals.lww.com
Aims: To clarify the decision-making and bereavement needs of family members who had
organ donation discussed with them; to provide a rationale for further preparation of …

On static test compaction and test pattern ordering for scan designs

X Lin, J Rajski, I Pomeranz… - … Test Conference 2001 …, 2001 - ieeexplore.ieee.org
A static compaction procedure to reduce test set size for scan designs and a procedure to
order test patterns in order to steepen the fault coverage curve are presented. The …

Test vector decomposition-based static compaction algorithms for combinational circuits

AH El-Maleh, YE Osais - ACM Transactions on Design Automation of …, 2003 - dl.acm.org
Testing system-on-chips involves applying huge amounts of test data, which is stored in the
tester memory and then transferred to the chip under test during test application. Therefore …

Ant-Line: a line-oriented ACO algorithm for the set covering problem

MH Mulati, AA Constantino - 2011 30th International …, 2011 - ieeexplore.ieee.org
This paper proposes the algorithm based on the metaheuristic Ant Colony Optimization
(ACO) called Ant-Line, which uses the line-oriented approach for the set covering problem …

Negotiated security policies for e-services and web services

G Yee, L Korba - … Conference on Web Services (ICWS'05), 2005 - ieeexplore.ieee.org
The growth of the Internet has been accompanied by the growth of e-services (eg e-
commerce, e-health). This proliferation of e-services and the increasing attacks on them by …

ZATPG: SAT-based test patterns generator with zero-aliasing in temporal compaction

R Hülle, P Fišer, J Schmidt - Microprocessors and Microsystems, 2018 - Elsevier
Aliasing in test response compaction is an important source of fault coverage loss. Methods
to avoid the aliasing mostly require modification of the compactor to some extent. This can …

Specification-based compaction of directed tests for functional validation of pipelined processors

HM Koo, P Mishra - Proceedings of the 6th IEEE/ACM/IFIP international …, 2008 - dl.acm.org
Functional validation is a major bottleneck in microprocessor design methodology.
Simulation is the widely used method for functional validation using billions of random and …

Static test compaction for scan circuits by using restoration to modify and remove tests

I Pomeranz - IEEE Transactions on Computer-Aided Design of …, 2014 - ieeexplore.ieee.org
This paper describes a new approach to static test compaction for scan circuits that modifies
tests in order to reduce the number of tests in a test set. The main contribution of this paper is …

A new method for test suite reduction

R Zhang, J Jiang, J Yin, A **, J Lou… - 2008 The 9th …, 2008 - ieeexplore.ieee.org
Test suite reduction is to find a subset of the test suite containing a minimal number of test
cases that can satisfy all test requirements. Test suite reduction techniques attempt to …