Seizing the bandwidth scaling of on-package interconnect in a post-Moore's law world

G Chirkov, D Wentzlaff - … of the 37th International Conference on …, 2023 - dl.acm.org
The slowing and forecasted end of Moore's Law have forced designers to look beyond
simply adding transistors, encouraging them to employ other unused resources as a manner …

Challenges and Opportunities in Future Multi-Chiplet Architectures

G Chirkov - 2024 - search.proquest.com
The slowdown of Moore's Law has decreased the rate that transistor density has been
increasing in silicon chips. These circumstances increasingly force computer architects to …

Optimising DRAM caches for latency in datacenter servers

A Shahab - 2024 - era.ed.ac.uk
The unyielding growth in the amount of data processed by datacenter servers warrants an
unabated increase in cache capacities. Modern servers already dedicate a big proportion of …

Adaptive Caching Policies for Chiplet Systems Based on Reinforcement Learning

C Yang, Z Zhang, X Wang, P Liu - 2023 IEEE International …, 2023 - ieeexplore.ieee.org
Chiplet packaging becomes a popular solution to integrate more hardware components.
However, shared memory access across chiplets suffers from high miss penalty due to long …

Adaptive invalidate/update coherence protocol with accurate prediction for all-private cache hierarchies

M Zhu - 2023 - era.ed.ac.uk
The cache hierarchy is critical in today's Chip Multiprocessors (CMPs), and Last-Level
Cache (LLC) is of particular interest to a modern cache hierarchy. LLC typically accounts for …

Evaluation of the Impact of Coherence Protocols and Cache Sizes on Parallel Algorithms Through Simulations

GDC Fagundes, MA Souza - Simpósio em Sistemas Computacionais …, 2024 - sol.sbc.org.br
This article explores the intersection between parallel algorithms and cache optimization,
focusing on how different coherence protocols and cache sizes impact the performance of …