Machine learning accelerators in 2.5 D chiplet platforms with silicon photonics
Domain-specific machine learning (ML) accelerators such as Google's TPU and Apple's
Neural Engine now dominate CPUs and GPUs for energy-efficient ML processing. However …
Neural Engine now dominate CPUs and GPUs for energy-efficient ML processing. However …
ReSiPI: A reconfigurable silicon-photonic 2.5 D chiplet network with PCMs for energy-efficient interposer communication
2.5 D chiplet systems have been proposed to improve the low manufacturing yield of large-
scale chips. However, connecting the chiplets through an electronic interposer imposes a …
scale chips. However, connecting the chiplets through an electronic interposer imposes a …
Swint: A non-blocking switch-based silicon photonic interposer network for 2.5 d machine learning accelerators
The surging demand for machine learning (ML) applications has emphasized the pressing
need for efficient ML accelerators capable of addressing the computational and energy …
need for efficient ML accelerators capable of addressing the computational and energy …
On the routing and scalability of mzi-based optical beneš interconnects
Silicon Photonic interconnects are a promising technology for scaling computing systems
into the exa-scale domain. However, there exist significant challenges in terms of optical …
into the exa-scale domain. However, there exist significant challenges in terms of optical …
Silicon Photonic 2.5 D Interposer Networks for Overcoming Communication Bottlenecks in Scale-out Machine Learning Hardware Accelerators
Modern machine learning (ML) applications are becoming increasingly complex and
monolithic (single chip) accelerator architectures cannot keep up with their energy efficiency …
monolithic (single chip) accelerator architectures cannot keep up with their energy efficiency …
Hta: A scalable high-throughput accelerator for irregular hpc workloads
We propose a new architecture called HTA for high throughput irregular HPC applications
with little data reuse. HTA reduces the contention within the memory system with the help of …
with little data reuse. HTA reduces the contention within the memory system with the help of …
Design and Optimization of Efficient, Fault-Tolerant and Secure 2.5 D Chiplet Systems
E Taheri - 2024 - search.proquest.com
In response to the burgeoning demand for high-performance computing systems, this Ph. D.
dissertation investigates the pivotal challenges surrounding Networks-on-Chip (NoCs) …
dissertation investigates the pivotal challenges surrounding Networks-on-Chip (NoCs) …
Decreasing latency considering power consumption issue in silicon interposer-based network-on-chip
Stacking technology is an approach to improve scalability of 2D network-on-chip systems.
3D stacking technology places multiple chips vertically, while silicon chips are stacked side …
3D stacking technology places multiple chips vertically, while silicon chips are stacked side …
[책][B] Scalable High Performance Memory Subsystem with Optical Interconnects
P Fotouhi - 2021 - search.proquest.com
Data movement has become a limiting factor in terms of performance, power consumption,
and scalability of high-performance compute nodes with increasing numbers of processor …
and scalability of high-performance compute nodes with increasing numbers of processor …