Highly optimized network-on-chip design at large scale
G Moran, G Koren, G Malach - US Patent 12,143,302, 2024 - Google Patents
There may be provided a method for traffic control in a network on chip (NOC), the method
may include receiving, by input interface units of the NOC, flow control units destined to …
may include receiving, by input interface units of the NOC, flow control units destined to …
Methods to extend noc interconnect across multiple dice in 3d
A Gupta, K Srinivasan, BC Gaide… - US Patent App. 18 …, 2024 - Google Patents
Embodiments herein describe techniques to extend a network-on-chip (NoC) across
multiple IC dice in 3D. An integrated circuit (IC) device includes first and second vertically …
multiple IC dice in 3D. An integrated circuit (IC) device includes first and second vertically …
Router architecture for multi-dimensional topologies in on-chip and on-package networks
T Suri, BS Sheikh, M Shak, N Zaman - US Patent 12,095,653, 2024 - Google Patents
A router may include input buffers that receive a packet being transmitted from a source to a
destination, a state generator that determines a state for the packet, and a memory …
destination, a state generator that determines a state for the packet, and a memory …