[КНИГА][B] Fault-tolerance techniques for SRAM-based FPGAs

This book presents fault-tolerant techniques for programmable architectures, the well-known
Field Programmable Gate Arrays (FPGAs), customizable by SRAM. FPGAs are becoming …

Matrix codes for reliable and cost efficient memory chips

C Argyrides, DK Pradhan… - IEEE Transactions on Very …, 2009 - ieeexplore.ieee.org
This paper presents a method to protect memories against multiple bit upsets and to improve
manufacturing yield. The proposed method, called a Matrix code, combines Hamming and …

A review on SEU mitigation techniques for FPGA configuration memory

TS Nidhin, A Bhattacharyya, RP Behera… - IETE Technical …, 2018 - Taylor & Francis
Single event upset (SEU) has become one of the major threats to dependable application
development targeted at safety systems in field programmable gate arrays (FPGAs). This …

Mitigating soft error failures for multimedia applications by selective data protection

K Lee, A Shrivastava, I Issenin, N Dutt… - Proceedings of the …, 2006 - dl.acm.org
With advances in process technology, soft errors (SE) are becoming an increasingly critical
design concern. Due to their large area and high density, caches are worst hit by soft errors …

[КНИГА][B] Resilient computer system design

V Castano, I Schagaev - 2015 - Springer
New areas of ICT applications require complete redesign of computer systems to address
challenges of extreme reliability, high performance and power efficiency. Up to now there …

An automatic technique for optimizing Reed-Solomon codes to improve fault tolerance in memories

G Neuberger… - IEEE Design & Test of …, 2005 - ieeexplore.ieee.org
Modern SoC architectures manufactured at ever-decreasing geometries use multiple
embedded memories. Error detection and correction codes are becoming increasingly …

Matrix-based codes for adjacent error correction

CA Argyrides, P Reviriego, DK Pradhan… - IEEE Transactions on …, 2010 - ieeexplore.ieee.org
Memories are one of the most widely used elements in electronic systems, and their
reliability when exposed to single events upsets (SEUs) has been studied extensively. As …

Designing of Reliable, Low-Power, and Performance-Efficient Onboard Computer Architecture for CubeSats

W Sajjad, A Shafique… - IEEE Journal on …, 2023 - ieeexplore.ieee.org
Technological innovations in small satellites especially CubeSats have become attractive
because of their low development cost and numerous applications, such as Earth remote …

Redundant residue number system code for fault-tolerant hybrid memories

NZ Haron, S Hamdioui - ACM journal on emerging technologies in …, 2011 - dl.acm.org
Hybrid memories are envisioned as one of the alternatives to existing semiconductor
memories. Although offering enormous data storage capacity, low power consumption, and …

Designing and testing fault-tolerant techniques for sram-based fpgas

FL Kastensmidt, G Neuberger, L Carro… - Proceedings of the 1st …, 2004 - dl.acm.org
This paper discusses fault-tolerant techniques for SRAM-based FPGAs. These techniques
can be based on circuit level modifications, with obvious modifications in the programmable …