Performance and computational complexity assessment of high-efficiency video encoders

G Correa, P Assuncao, L Agostini… - IEEE Transactions on …, 2012 - ieeexplore.ieee.org
This paper presents a performance evaluation study of coding efficiency versus
computational complexity for the forthcoming High Efficiency Video Coding (HEVC) …

Sparse unsupervised dimensionality reduction for multiple view data

Y Han, F Wu, D Tao, J Shao… - IEEE Transactions on …, 2012 - ieeexplore.ieee.org
Different kinds of high-dimensional visual features can be extracted from a single image.
Images can thus be treated as multiple view data when taking each type of extracted high …

Application of swarm intelligence techniques to the design of analog circuits: evaluation and comparison

A Sallem, B Benhala, M Kotti, M Fakhfakh… - … Integrated Circuits and …, 2013 - Springer
Swarm intelligence (SI) techniques are more and more used by analog designers in order to
optimally size their circuits/systems' performances. A particular interest is accorded to the …

Rate-distortion-complexity modeling for network and receiver aware adaptation

M Van Der Schaar… - IEEE Transactions on …, 2005 - ieeexplore.ieee.org
Existing research on Universal Multimedia Access has mainly focused on adapting
multimedia to the network characteristics while overlooking the receiver capabilities …

Hardware-efficient realization of prime-length DCT based on distributed arithmetic

J **e, PK Meher, J He - IEEE Transactions on Computers, 2012 - ieeexplore.ieee.org
This paper presents an efficient decomposition scheme for hardware-efficient realization of
discrete cosine transform (DCT) based on distributed arithmetic. We have proposed an …

Dynamic control of motion estimation search parameters for low complex H. 264 video coding

S Saponara, M Casula, F Rovati… - IEEE Transactions …, 2006 - ieeexplore.ieee.org
This paper presents a novel technique to reduce the motion estimation (ME) complexity in H.
264/AVC video coding. A low complexity context-aware controller is added to a basic search …

A multi-processor NoC-based architecture for real-time image/video enhancement

S Saponara, L Fanucci, E Petri - Journal of Real-Time Image Processing, 2013 - Springer
The paper presents a multi-processor architecture for real-time and low-power image and
video enhancement applications. Differently from other state-of-the-art parallel architectures …

Motion estimation and CABAC VLSI co-processors for real-time high-quality H. 264/AVC video coding

S Saponara, M Martina, M Casula, L Fanucci… - Microprocessors and …, 2010 - Elsevier
Real-time and high-quality video coding is gaining a wide interest in the research and
industrial community for different applications. H. 264/AVC, a recent standard for high …

A 1080p H. 264/AVC baseline residual encoder for a fine-grained many-core system

Z **ao, BM Baas - IEEE transactions on circuits and systems for …, 2011 - ieeexplore.ieee.org
This paper presents a baseline residual encoder for H. 264/AVC on a programmable fine-
grained many-core processing array that utilizes no application-specific hardware. The …

Design and coverage-driven verification of a novel network-interface IP macrocell for network-on-chip interconnects

S Saponara, L Fanucci, M Coppola - Microprocessors and Microsystems, 2011 - Elsevier
The work presents a configurable network interface (NI) macrocell to be integrated in
Spidergon network-on-chip (NoC) infrastructures, and addresses the problem of its …