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A modified CLTdSCR with low leakage and low capacitance for ESD protection
K Sun, T Li, L Meng - IEEE Transactions on Electron Devices, 2021 - ieeexplore.ieee.org
A modified cross-coupling low-triggering dual-polarity silicon controlled rectifier (-CLTdSCR)
for on-chip electrostatic discharge (ESD) protection is developed. Cross-coupling …
for on-chip electrostatic discharge (ESD) protection is developed. Cross-coupling …
Design and optimization of DTSCR for high-speed I/O ESD protection of on-chip ICs
H Liang, Y Yang, J Sun, J Liu, X Cao… - … Science and Technology, 2022 - iopscience.iop.org
A gate-assisted and diode-triggered silicon controlled rectifier with the waffle layout
(GDTSCR-WL) is proposed and investigated. By designing the waffle layout in the …
(GDTSCR-WL) is proposed and investigated. By designing the waffle layout in the …
On the ESD protection and non-fatal ESD strike on nano CMOS devices
Electrostatic discharge (ESD) has been one of the major causes for the failure of electronic
equipment and components and have attracted quite significant research efforts in …
equipment and components and have attracted quite significant research efforts in …
Design and Optimization of RC Triggered MV-NMOS for 28NM CMOS Technology ESD Protection
J Zhu, L Wei, Y Li, J Wu, K Wang… - 2023 China …, 2023 - ieeexplore.ieee.org
An effective design of RC triggered medium voltage ESD nMOS power clamp in 28nm high
voltage CMOS technology is presented in this work. Through transmission line plus test, it is …
voltage CMOS technology is presented in this work. Through transmission line plus test, it is …
A PNP-triggered dynamic substrate GGNMOS with improved performances
KM Sun, T Li, LY Meng - Solid-State Electronics, 2020 - Elsevier
A novel PNP-triggered dynamic substrate GGNMOS (gate-grounded NMOS) structure is
proposed and verified in 0.18 μm salicided CMOS process. Owing to the dynamic substrate …
proposed and verified in 0.18 μm salicided CMOS process. Owing to the dynamic substrate …
A novel area-efficiency multi-finger GGnMOS with high ESD robustness
C Zhang, S Liu, W Sun, L Shi - Solid-State Electronics, 2015 - Elsevier
For the multi-finger gate-grounded n-type MOS (GGnMOS) design, a large ballast resistance
is generally needed to overcome the non-uniform turn-on problem under electrostatic …
is generally needed to overcome the non-uniform turn-on problem under electrostatic …
Design and analysis of different trigger techniques for ESD clamp circuit in 0.5-µm 5 V/18 V CDMOS process
W Zhang, L Yang, Y Wang, X ** - Solid-State Electronics, 2017 - Elsevier
In this work, gate-driven, substrate-triggered and gate-substrate-triggered techniques for
both 5 V NMOS-based and 18 V NLDMOS-based power clamps under electrostatic …
both 5 V NMOS-based and 18 V NLDMOS-based power clamps under electrostatic …
ESD and LU Immunities of LV nMOSFETs by the Drain-Contact Variations
SL Chen, MH Lee - Advanced Materials Research, 2013 - Trans Tech Publ
The non-uniform turned-on issue of a multi-finger GGnMOS is deeply affect the ESD
robustness. This paper introduces a drain-side engineering: by removing the drain contacts …
robustness. This paper introduces a drain-side engineering: by removing the drain contacts …