Data prefetch mechanisms
The expanding gap between microprocessor and DRAM performance has necessitated the
use of increasingly aggressive techniques designed to reduce or hide the latency of main …
use of increasingly aggressive techniques designed to reduce or hide the latency of main …
A survey of recent prefetching techniques for processor caches
S Mittal - ACM Computing Surveys (CSUR), 2016 - dl.acm.org
As the trends of process scaling make memory systems an even more crucial bottleneck, the
importance of latency hiding techniques such as prefetching grows further. However, naively …
importance of latency hiding techniques such as prefetching grows further. However, naively …
[ΒΙΒΛΙΟ][B] Computer architecture: a quantitative approach
JL Hennessy, DA Patterson - 2011 - books.google.com
Computer Architecture: A Quantitative Approach, Fifth Edition, explores the ways that
software and technology in the cloud are accessed by digital media, such as cell phones …
software and technology in the cloud are accessed by digital media, such as cell phones …
[ΒΙΒΛΙΟ][B] Modern compiler implementation in ML
AW Appel - 1998 - books.google.com
This new, expanded textbook describes all phases of a modern compiler: lexical analysis,
parsing, abstract syntax, semantic actions, intermediate representations, instruction …
parsing, abstract syntax, semantic actions, intermediate representations, instruction …
[ΒΙΒΛΙΟ][B] Memory systems: cache, DRAM, disk
B Jacob, D Wang, S Ng - 2010 - books.google.com
Is your memory hierarchy stop** your microprocessor from performing at the high level it
should be? Memory Systems: Cache, DRAM, Disk shows you how to resolve this problem …
should be? Memory Systems: Cache, DRAM, Disk shows you how to resolve this problem …
SPIRAL: Code generation for DSP transforms
Fast changing, increasingly complex, and diverse computing platforms pose central
problems in scientific computing: How to achieve, with reasonable effort, portable optimal …
problems in scientific computing: How to achieve, with reasonable effort, portable optimal …
Effective hardware-based data prefetching for high-performance processors
TF Chen, JL Baer - IEEE transactions on computers, 1995 - ieeexplore.ieee.org
Memory latency and bandwidth are progressing at a much slower pace than processor
performance. In this paper, we describe and evaluate the performance of three variations of …
performance. In this paper, we describe and evaluate the performance of three variations of …
Value locality and load value prediction
Since the introduction of virtual memory demand-paging and cache memories, computer
systems have been exploiting spatial and temporal locality to reduce the average latency of …
systems have been exploiting spatial and temporal locality to reduce the average latency of …
Prefetching using markov predictors
D Joseph, D Grunwald - Proceedings of the 24th annual international …, 1997 - dl.acm.org
Prefetching is one approach to reducing the latency of memory operations in modern
computer systems. In this paper, we describe the Markov prefetcher. This prefetcher acts as …
computer systems. In this paper, we describe the Markov prefetcher. This prefetcher acts as …
Runahead execution: An alternative to very large instruction windows for out-of-order processors
Today's high performance processors tolerate long latency operations by means of out-of-
order execution. However, as latencies increase, the size of the instruction window must …
order execution. However, as latencies increase, the size of the instruction window must …