This paper describes the polymorphous TRIPS architecture which can be configured for
different granularities and types of parallelism. TRIPS contains mechanisms that enable the …

While architects understand how to build cost-effective parallel machines across a wide
spectrum of machine sizes (ranging from within a single chip to large-scale servers), the real …

Transactional Memory (TM), Thread-Level Speculation (TLS), and Checkpointed
multiprocessors are three popular architectural techniques based on the execution of …

We develop an availability solution, called SafetyNet, that uses a unified, lightweight
checkpoint/recovery mechanism to support multiple long-latency fault detection schemes. At …

High performance parallel programs are currently difficult to write and debug. One major
source of difficulty is protecting concurrent accesses to shared data with an appropriate …

In today's widely used parallel programming models, subtle programming errors can lead to
unintended nondeterministic behavior and hard to catch bugs. In contrast, we argue for a …

Thread-Level Speculation (TLS) is a promising technique that allows the parallel execution
of sequential code without relying on a prior, compile-time-dependence analysis. In this …

Barriers, locks, and flags are synchronizing operations widely used programmers and
parallelizing compilers to produce race-free parallel programs. Often times, these operations …

Multithreaded processor architectures are becoming increasingly commonplace: many
current and upcoming designs support chip multiprocessing, simultaneous multithreading …

Speculative parallelization can provide significant sources of additional thread-level
parallelism, especially for irregular applications that are hard to parallelize by conventional …