A global clock distribution strategy used on several microprocessor chips is described. The
clock network consists of buffered tunable trees or treelike networks, with the final level of …

Provides the only up-to-date source on the most recent advances in this often complex and
fascinating topic. The only book to be entirely devoted to clocking Clocking has become one …

The decrease in feature size and added chip functionality in large sub-micron integrated
circuits demand larger grids for power distribution. Since power grids are performance …

A global clock network that incorporates standing waves and coupled oscillators to distribute
a high-frequency clock signal with low skew and low jitter is described. The key design …

A new dual edge-triggered flip-flop that saves power by inhibiting transitions of the nodes
that are not used to change the state is presented. The proposed flip-flop is 12% faster with …

Due to the large die sizes and tight relative clock skew margins, the impact of interconnect
manufacturing variations on the clock skew in today's gigahertz microprocessors can no …

There is arguably no field in greater need of a comprehensive handbook than computer
engineering. The unparalleled rate of technological advancement, the explosion of …

As advances in technology and circuit design boost operating frequencies of
microprocessors, DSPs and other fast chips, new design challenges continue to emerge …

This paper describes the classification, detailed timing characterization, evaluation, and
design of the dual-edge triggered storage elements (DETSE). The performance and power …

A summary of electrical and optical approaches to clock distribution within high-performance
microprocessors is presented. System-level properties of intrachip electrical clock …