In the proposed work, a differential write and single-ended read half-select free 12
transistors static random access memory cell is designed and simulated. The proposed cell …

Chip aging that results in small delay defects is one of the possible causes for silent data
corruption that has been observed in large datacenters. Chip aging is exacerbated by high …

High workloads applied to a system cause chips to be more susceptible to aging effects that
may eventually result in hardware defects. The detection of the defects requires tests for …

Motivated by the reliability requirements of chips in state-of-the-art technologies, this article
develops an approach to periodic in-field testing that has the following features. The faults …

Although DRAM capacity and bandwidth have increased sharply by the advances in
technology and standards, its latency and energy per access have remained almost …

Technology scaling has exacerbated the aging impact on the performance and reliability of
integrated circuits. By entering into nanotechnology era in recent years, the power density …

State-of-the-art designs include identical instances of logic blocks to support parallel
computations. Identical logic blocks at close physical proximity can be tested online by …

This paper proposes an enhanced cache organization to mitigate the coherence-induced
static noise margin degradation of cache memory cells. The enhancement is conducted …

Cache memories dissipate a large portion of processors' power budget. On the other hand,
due to unbalanced stress condition on their SRAMs, aging of cache memories is one of the …