The Understanding and Compact Modeling of Reliability in Modern Metal–Oxide–Semiconductor Field-Effect Transistors: From Single-Mode to Mixed-Mode …

Z Sun, S Chen, L Zhang, R Huang, R Wang - Micromachines, 2024 - mdpi.com
With the technological scaling of metal–oxide–semiconductor field-effect transistors
(MOSFETs) and the scarcity of circuit design margins, the characteristics of device reliability …

Design for manufacturability and reliability in extreme-scaling VLSI

B Yu, X Xu, S Roy, Y Lin, J Ou, DZ Pan - Science China Information …, 2016 - Springer
In the last five decades, the number of transistors on a chip has increased exponentially in
accordance with the Moore's law, and the semiconductor industry has followed this law as …

A novel majority based imprecise 4: 2 compressor with respect to the current and future VLSI industry

MR Taheri, A Arasteh, S Mohammadyan… - Microprocessors and …, 2020 - Elsevier
Imprecising the arithmetic hardware blocks is well known as one of the brilliant approaches
that increase the performance of digital signal processors (DSP) at the cost of imposing …

Towards reliability-aware circuit design in nanoscale FinFET technology:—New-generation aging model and circuit reliability simulator

S Guo, R Wang, Z Yu, P Hao, P Ren… - 2017 IEEE/ACM …, 2017 - ieeexplore.ieee.org
In this paper, an industry-level new-generation EDA solution for reliability-aware design in
nanoscale FinFET technology is presented for the first time, with new compact transistor …

CAD for Analog/Mixed‐Signal Integrated Circuits

AF Budak, DZ Pan, H Chen, K Zhu… - Advances in …, 2022 - Wiley Online Library
While digital integrated circuits (ICs) has adopted highly automated computer aided design
(CAD) tools for decades including synthesis, placement, and routing, analog, and mixed …

Reliable and high performance asymmetric FinFET SRAM cell using back-gate control

RN Asli, S Taghipour - Microelectronics Reliability, 2020 - Elsevier
As the technology scales down, the performance characteristics are degraded and the
reliability of digital circuits against soft error and aging effects are reduced. In this paper, we …

Uniform non-Bernoulli sequences oriented locating method for reliability-critical gates

J **ao, Z Shi, W Zhu, J Jiang, Q Zhou… - Tsinghua Science …, 2020 - ieeexplore.ieee.org
Hardening reliability-critical gates in a circuit is an important step to improve the circuit
reliability at a low cost. However, accurately locating the reliability-critical gates is a key …

Wages: The Worst Transistor Aging Analysis for Large-scale Analog Integrated Circuits via Domain Generalization

T Chen, H Geng, Q Sun, S Wan, Y Sun, H Yu… - ACM Transactions on …, 2024 - dl.acm.org
Transistor aging leads to the deterioration of analog circuit performance over time. The worst
aging degradation is used to evaluate the circuit reliability. It is extremely expensive to …

Aging-Aware Critical Path Selection via Graph Attention Networks

Y Ye, T Chen, Y Gao, H Yan, B Yu… - IEEE Transactions on …, 2023 - ieeexplore.ieee.org
In advanced technology nodes, aging effects like negative and positive bias temperature
instability (NBTI and PBTI) become increasingly significant, making timing closure and …

Work hard, sleep well-avoid irreversible ic wearout with proactive rejuvenation

X Guo, MR Stan - 2016 21st Asia and South Pacific Design …, 2016 - ieeexplore.ieee.org
Various wearout mechanisms have both a reversible and an irreversible (permanent) part,
with some, like BTI and EM having a significant reversible part, while others, like HCI, being …