Silicon–germanium nanowires: chemistry and physics in play, from basic principles to advanced applications

M Amato, M Palummo, R Rurali, S Ossicini - Chemical reviews, 2014 - ACS Publications
The trend predicted by Moore's law sets forth strict requirements on the electronic properties
of materials that cannot always be satisfied by conventional semiconductors. Thus, the last …

Functional devices from bottom-up Silicon nanowires: A review

T Arjmand, M Legallais, TTT Nguyen, P Serre… - Nanomaterials, 2022 - mdpi.com
This paper summarizes some of the essential aspects for the fabrication of functional
devices from bottom-up silicon nanowires. In a first part, the different ways of exploiting …

Strain-gated piezotronic transistors based on vertical zinc oxide nanowires

W Han, Y Zhou, Y Zhang, CY Chen, L Lin, X Wang… - ACS …, 2012 - ACS Publications
Strain-gated piezotronic transistors have been fabricated using vertically aligned ZnO
nanowires (NWs), which were grown on GaN/sapphire substrates using a vapor–liquid …

Toward monolithic growth integration of nanowire electronics in 3D architecture: a review

L Liang, R Hu, L Yu - Science China Information Sciences, 2023 - Springer
Abstract Quasi-one-dimensional (1D) semiconducting nanowires (NWs), with excellent
electrostatic control capability, are widely regarded as advantageous channels for the …

Vertical Ge/Si core/shell nanowire junctionless transistor

L Chen, F Cai, U Otuonye, WD Lu - Nano Letters, 2016 - ACS Publications
Vertical junctionless transistors with a gate-all-around (GAA) structure based on Ge/Si
core/shell nanowires epitaxially grown and integrated on a⟨ 111⟩ Si substrate were …

Material engineering of percolating silicon nanowire networks for reliable and efficient electronic devices

M Legallais, TTT Nguyen, T Cazimajou, M Mouis… - Materials Chemistry and …, 2019 - Elsevier
Motivated to produce reliable and performant SiNW-based transistors, we present in this
work how percolating networks composed of randomly oriented SiNWs, called nanonets, are …

Fabrication and characterization of silicon nanowire pin MOS gated diode for use as p-type tunnel FET

V Brouzet, B Salem, P Periwal, G Rosaz, T Baron… - Applied Physics A, 2015 - Springer
In this paper, we present the fabrication and electrical characterization of a MOS gated diode
based on axially doped silicon nanowire (NW) pin junctions. These nanowires are grown by …

Current transport mechanism at metal–semiconductor nanoscale interfaces based on ultrahigh density arrays of p-type NiO nano-pillars

S Nandy, G Gonçalves, JV Pinto, T Busani… - Nanoscale, 2013 - pubs.rsc.org
The present work focuses on a qualitative analysis of localised I–V characteristics based on
the nanostructure morphology of highly dense arrays of p-type NiO nano-pillars (NiO-NPs) …

On Demand Shape-Selective Integration of Individual Vertical Germanium Nanowires on a Si(111) Substrate via Laser-Localized Heating

S Ryu, E Kim, J Yoo, DJ Hwang, B **ang, OD Dubon… - ACS …, 2013 - ACS Publications
Semiconductor nanowire (NW) synthesis methods by blanket furnace heating produce
structures of uniform size and shape. This study overcomes this constraint by applying laser …

Wireless Interconnect using Inductive Coupling in 3D-ICs.

SW Han - 2012 - deepblue.lib.umich.edu
The mobile market is growing rapidly, as is the demand for high performance and multiple
functions in a single device. 3D integration is a promising solution for integrating …