Testability and dependability of AI hardware: Survey, trends, challenges, and perspectives

F Su, C Liu, HG Stratigopoulos - IEEE Design & Test, 2023 - ieeexplore.ieee.org
Hardware realization of artificial intelligence (AI) requires new design styles and even
underlying technologies than those used in traditional digital processors or logic circuits …

Neural coding in spiking neural networks: A comparative study for robust neuromorphic systems

W Guo, ME Fouda, AM Eltawil… - Frontiers in Neuroscience, 2021 - frontiersin.org
Various hypotheses of information representation in brain, referred to as neural codes, have
been proposed to explain the information transmission between neurons. Neural coding …

[PDF][PDF] Memory built-in self-repair and correction for improving yield: a review

V Sontakke, D Atchina - International Journal of Electrical and …, 2024 - academia.edu
Nanometer memories are highly prone to defects due to dense structure, necessitating
memory built-in self-repair as a must-have feature to improve yield. Today's system-on-chips …

Defects, fault modeling, and test development framework for RRAMs

M Fieback, GC Medeiros, L Wu, H Aziza… - ACM Journal on …, 2022 - dl.acm.org
Resistive RAM (RRAM) is a promising technology to replace traditional technologies such
as Flash, because of its low energy consumption, CMOS compatibility, and high density …

Low-power memristor-based computing for edge-AI applications

A Singh, S Diware, A Gebregiorgis… - … on Circuits and …, 2021 - ieeexplore.ieee.org
With the rise of the Internet of Things (IoT), a huge market for so-called smart edge-devices
is foreseen for millions of applications, like personalized healthcare and smart robotics …

Electrical modeling of STT-MRAM defects

L Wu, M Taouil, S Rao, EJ Marinissen… - … Test Conference (ITC …, 2018 - ieeexplore.ieee.org
Spin-transfer-torque magnetic RAM (STT-MRAM) is one of the most promising emerging
memory technologies. As various manufacturing vendors make significant efforts to push it to …

Special session: Reliability of hardware-implemented spiking neural networks (SNN)

EI Vatajelu, G Di Natale… - 2019 IEEE 37th VLSI Test …, 2019 - ieeexplore.ieee.org
The research work presented in this paper deals with the fault analysis in hardware-
implemented Spiking Neural Networks with special emphasis on circuits designed to …

Review of manufacturing process defects and their effects on memristive devices

LMB Poehls, MCR Fieback, S Hoffmann-Eifert… - Journal of electronic …, 2021 - Springer
Abstract Complementary Metal Oxide Semiconductor (CMOS) technology has been scaled
down over the last forty years making possible the design of high-performance applications …

Dealing with non-idealities in memristor based computation-in-memory designs

A Gebregiorgis, A Singh, S Diware… - 2022 IFIP/IEEE 30th …, 2022 - ieeexplore.ieee.org
Computation-In-Memory (CIM) using memristor devices provides an energy-efficient
hardware implementation of arithmetic and logic operations for numerous applications, such …

TA-LRW: A replacement policy for error rate reduction in STT-MRAM caches

E Cheshmikhani, H Farbeh… - IEEE Transactions on …, 2018 - ieeexplore.ieee.org
As technology process node scales down, on-chip SRAM caches lose their efficiency
because of their low scalability, high leakage power, and increasing rate of soft errors …