Recent progress and challenges regarding carbon nanotube on-chip interconnects

B Xu, R Chen, J Zhou, J Liang - Micromachines, 2022 - mdpi.com
Along with deep scaling transistors and complex electronics information exchange networks,
very-large-scale-integrated (VLSI) circuits require high performance and ultra-low power …

[BUKU][B] On-chip communication architectures: system on chip interconnect

S Pasricha, N Dutt - 2010 - books.google.com
Over the past decade, system-on-chip (SoC) designs have evolved to address the ever
increasing complexity of applications, fueled by the era of digital convergence …

Clock distribution networks in synchronous digital integrated circuits

EG Friedman - Proceedings of the IEEE, 2001 - ieeexplore.ieee.org
Clock distribution networks synchronize the flow of data signals among synchronous data
paths. The design of these networks can dramatically affect system-wide performance and …

On-chip optical interconnect roadmap: Challenges and critical directions

M Haurylau, G Chen, H Chen, J Zhang… - IEEE Journal of …, 2006 - ieeexplore.ieee.org
Intrachip optical interconnects (OIs) have the potential to outperform electrical wires and to
ultimately solve the communication bottleneck in high-performance integrated circuits …

Mini-review: Modeling and performance analysis of nanocarbon interconnects

WS Zhao, K Fu, DW Wang, M Li, G Wang, WY Yin - Applied Sciences, 2019 - mdpi.com
As the interconnect delay exceeds the gate delay, the integrated circuit (IC) technology has
evolved from a transistor-centric era to an interconnect-centric era. Conventional metallic …

Predictions of CMOS compatible on-chip optical interconnect

G Chen, H Chen, M Haurylau, N Nelson… - Proceedings of the …, 2005 - dl.acm.org
Interconnect has become a primary bottleneck in integrated circuit design. As CMOS
technology is scaled, it will become increasingly difficult for conventional copper …

Analysis of on-chip inductance effects for distributed RLC interconnects

K Banerjee, A Mehrotra - IEEE Transactions on computer …, 2002 - ieeexplore.ieee.org
This paper introduces an accurate analysis of on-chip inductance effects for distributed RLC
interconnects that takes the effect of both the series resistance and the output parasitic …

[BUKU][B] Managing temperature effects in nanoscale adaptive systems

D Wolpert, P Ampadu - 2011 - books.google.com
This book discusses new techniques for detecting, controlling, and exploiting the impacts of
temperature variations on nanoscale circuits and systems. A new sensor system is …

The challenge of signal integrity in deep-submicrometer CMOS technology

F Caignet, S Delmas-Bendhia… - Proceedings of the …, 2001 - ieeexplore.ieee.org
Advances in interconnect technologies, such as the increase in the number of metal layers,
stacked vias, and the reduced routing pitch, have played a key role to continuously improve …

Fast transient analysis of next-generation interconnects based on carbon nanotubes

M D'Amore, MS Sarto… - IEEE Transactions on …, 2010 - ieeexplore.ieee.org
The scaling of copper wires and the increase in signal switching speed produce transient
crosstalk coupling between interconnect lines, which causes overshoots and additional time …