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Recent progress and challenges regarding carbon nanotube on-chip interconnects
Along with deep scaling transistors and complex electronics information exchange networks,
very-large-scale-integrated (VLSI) circuits require high performance and ultra-low power …
very-large-scale-integrated (VLSI) circuits require high performance and ultra-low power …
[BUKU][B] On-chip communication architectures: system on chip interconnect
S Pasricha, N Dutt - 2010 - books.google.com
Over the past decade, system-on-chip (SoC) designs have evolved to address the ever
increasing complexity of applications, fueled by the era of digital convergence …
increasing complexity of applications, fueled by the era of digital convergence …
Clock distribution networks in synchronous digital integrated circuits
EG Friedman - Proceedings of the IEEE, 2001 - ieeexplore.ieee.org
Clock distribution networks synchronize the flow of data signals among synchronous data
paths. The design of these networks can dramatically affect system-wide performance and …
paths. The design of these networks can dramatically affect system-wide performance and …
On-chip optical interconnect roadmap: Challenges and critical directions
Intrachip optical interconnects (OIs) have the potential to outperform electrical wires and to
ultimately solve the communication bottleneck in high-performance integrated circuits …
ultimately solve the communication bottleneck in high-performance integrated circuits …
Mini-review: Modeling and performance analysis of nanocarbon interconnects
As the interconnect delay exceeds the gate delay, the integrated circuit (IC) technology has
evolved from a transistor-centric era to an interconnect-centric era. Conventional metallic …
evolved from a transistor-centric era to an interconnect-centric era. Conventional metallic …
Predictions of CMOS compatible on-chip optical interconnect
Interconnect has become a primary bottleneck in integrated circuit design. As CMOS
technology is scaled, it will become increasingly difficult for conventional copper …
technology is scaled, it will become increasingly difficult for conventional copper …
Analysis of on-chip inductance effects for distributed RLC interconnects
K Banerjee, A Mehrotra - IEEE Transactions on computer …, 2002 - ieeexplore.ieee.org
This paper introduces an accurate analysis of on-chip inductance effects for distributed RLC
interconnects that takes the effect of both the series resistance and the output parasitic …
interconnects that takes the effect of both the series resistance and the output parasitic …
[BUKU][B] Managing temperature effects in nanoscale adaptive systems
This book discusses new techniques for detecting, controlling, and exploiting the impacts of
temperature variations on nanoscale circuits and systems. A new sensor system is …
temperature variations on nanoscale circuits and systems. A new sensor system is …
The challenge of signal integrity in deep-submicrometer CMOS technology
F Caignet, S Delmas-Bendhia… - Proceedings of the …, 2001 - ieeexplore.ieee.org
Advances in interconnect technologies, such as the increase in the number of metal layers,
stacked vias, and the reduced routing pitch, have played a key role to continuously improve …
stacked vias, and the reduced routing pitch, have played a key role to continuously improve …
Fast transient analysis of next-generation interconnects based on carbon nanotubes
The scaling of copper wires and the increase in signal switching speed produce transient
crosstalk coupling between interconnect lines, which causes overshoots and additional time …
crosstalk coupling between interconnect lines, which causes overshoots and additional time …