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How to control defect formation in monolithic III/V hetero-epitaxy on (100) Si? A critical review on current approaches
B Kunert, Y Mols, M Baryshniskova… - Semiconductor …, 2018 - iopscience.iop.org
The monolithic hetero-integration of III/V materials on Si substrates could enable a multitude
of new device applications and functionalities which would benefit from both the excellent …
of new device applications and functionalities which would benefit from both the excellent …
Epitaxial growth of highly mismatched III-V materials on (001) silicon for electronics and optoelectronics
Monolithic integration of III-V on silicon has been a scientifically appealing concept for
decades. Notable progress has recently been made in this research area, fueled by …
decades. Notable progress has recently been made in this research area, fueled by …
Room-temperature InP distributed feedback laser array directly grown on silicon
Z Wang, B Tian, M Pantouvaki, W Guo, P Absil… - Nature …, 2015 - nature.com
Fully exploiting the silicon photonics platform for large-volume, cost-sensitive applications
requires a fundamentally new approach to directly integrate high-performance laser sources …
requires a fundamentally new approach to directly integrate high-performance laser sources …
Total-Ionizing-Dose Effects, Border Traps, and 1/f Noise in Emerging MOS Technologies
DM Fleetwood - IEEE Transactions on Nuclear Science, 2020 - ieeexplore.ieee.org
Subthreshold leakage currents and threshold-voltage shifts due to total-ionizing-dose (TID)
irradiation are reviewed briefly for highly scaled devices in emerging MOS technologies …
irradiation are reviewed briefly for highly scaled devices in emerging MOS technologies …
InGaAs gate-all-around nanowire devices on 300mm Si substrates
In this letter, we present the first InGaAs gate-all-around (GAA) nanowire devices fabricated
on 300mm Si substrates. For an LG of 60 nm an extrinsic gm of 1030 μS/μm at V ds= 0.5 V is …
on 300mm Si substrates. For an LG of 60 nm an extrinsic gm of 1030 μS/μm at V ds= 0.5 V is …
Nanometer-Scale III-V MOSFETs
JA Del Alamo, DA Antoniadis, J Lin… - IEEE Journal of the …, 2016 - ieeexplore.ieee.org
After 50 years of Moore's Law, Si CMOS, the mainstream logic technology, is on a course of
diminishing returns. The use of new semiconductor channel materials with improved …
diminishing returns. The use of new semiconductor channel materials with improved …
[CARTE][B] Metrology and Diagnostic Techniques for Nanoelectronics
Z Ma, DG Seiler - 2017 - taylorfrancis.com
Nanoelectronics is changing the way the world communicates, and is transforming our daily
lives. Continuing Moore's law and miniaturization of low-power semiconductor chips with …
lives. Continuing Moore's law and miniaturization of low-power semiconductor chips with …
The impact of fin number on device performance and reliability for multi-fin tri-gate n-and p-type FinFET
WK Yeh, W Zhang, PY Chen… - IEEE Transactions on …, 2018 - ieeexplore.ieee.org
In this paper, the effect of carrier quantization on device characteristics and stress-induced
device degradation for multifin high-κ/metal tri-gate n-type and p-type fin field-effect …
device degradation for multifin high-κ/metal tri-gate n-type and p-type fin field-effect …
Total-Ionizing-Dose Effects and Low-Frequency Noise in 16-nm InGaAs FinFETs With HfO2/Al2O3 Dielectrics
Total-ionizing-dose mechanisms are investigated in 16-nm InGaAs FinFETs with an HfO 2/Al
2 O 3 gate-stack. Transistors are irradiated up to 500 krad (SiO 2) and annealed at high …
2 O 3 gate-stack. Transistors are irradiated up to 500 krad (SiO 2) and annealed at high …
Sub-10-nm fin-width self-aligned InGaAs FinFETs
We study the scaling properties of self-aligned InGaAs FinFETs with sub-10-nm fin widths
fabricated through a CMOS compatible front-end process. Working devices with fins as …
fabricated through a CMOS compatible front-end process. Working devices with fins as …