Given the significance of placement in IC physical design, extensive research studies
performed over the last 50 years addressed numerous aspects of global and detailed …

Dual-supply voltage design using a clustered voltage scaling (CVS) scheme is an effective
approach to reduce chip power. The optimal CVS design relies on a level converter (LC) …

Traditional FPGAs use uniform supply voltage Vdd and uniform threshold voltage Vt. We
propose to use pre-defined dual-Vdd and dual-Vt fabrics to reduce FPGA power. We design …

Subthreshold digital circuits minimize energy per operation and are thus ideal for ultralow-
power (ULP) applications with low performance requirements. However, a large range of …

We propose a deep convolutional neural network (CNN) inference processor based on a
novel enhanced output stationary (EOS) dataflow. Based on the observation that some …

Multi-V/sub DD/design is an effective way to reduce power consumption, but the need for
level conversion imposes delay and energy penalties that limit the potential gains. In this …

Power Gating has become one of the most widely used circuit design techniques for
reducing leakage current. Its concept is very simple, but its application to standard-cell VLSI …

Two novel level shifters that are suitable for block-level dynamic voltage scaling
environment (namely, V/sub DD/-hop**) are proposed. In order to achieve reduction in …

In the deep sub-micron regime, the power consumption has become one of the most
important issues for competitive design of digital circuits. Due to dramatically increasing …

Low-Power High-Level Synthesis for Nanoscale CMOS Circuits addresses the need for
analysis, characterization, estimation, and optimization of the various forms of power …