[BOOK][B] VLSI test principles and architectures: design for testability
This book is a comprehensive guide to new DFT methods that will show the readers how to
design a testable and quality product, drive down test cost, improve product quality and …
design a testable and quality product, drive down test cost, improve product quality and …
An amalgamated testability measure derived from machine intelligence
A testability measure provides test-related information about signal nodes of a circuit.
Operations like test generation and test point insertion are exponentially complex in terms of …
Operations like test generation and test point insertion are exponentially complex in terms of …
Nimrod/K: towards massively parallel dynamic grid workflows
A challenge for Grid computing is the difficulty in develo** software that is parallel,
distributed and highly dynamic. Whilst there have been many general purpose mechanisms …
distributed and highly dynamic. Whilst there have been many general purpose mechanisms …
Method for testability analysis and test point insertion at the RT-level of a hardware development language (HDL) specification
S Boubezari, E Cerny, B Kaminska… - US Patent …, 2002 - Google Patents
A method is provided for producing a synthesizable RT-Level specification, having a
testability enhancement from a starting RT-Level specification representative of a circuit to …
testability enhancement from a starting RT-Level specification representative of a circuit to …
Towards understanding how developers spend their effort during maintenance activities
For many years, researchers and practitioners have strived to assess and improve the
productivity of software development teams. One key step toward achieving this goal is the …
productivity of software development teams. One key step toward achieving this goal is the …
[PDF][PDF] Behavioral synthesis of highly testable data paths under the non-scan and partial scan environments
Behauzorai synthesis tools which only optimize area and performance can easily produce a
hard-to-test archit ecture. In this paper, we propose a new behavioral synthesis algorithm for …
hard-to-test archit ecture. In this paper, we propose a new behavioral synthesis algorithm for …
Behavioral synthesis for easy testability in data path scheduling
Lee, Jha - 1992 IEEE/ACM International Conference on …, 1992 - ieeexplore.ieee.org
A data path scheduling algorithm to improve testability without assuming any particular test
strategy is presented. A scheduling heuristic for easy testability, based on previous work on …
strategy is presented. A scheduling heuristic for easy testability, based on previous work on …
Incorporating testability considerations in high-level synthesis
A Mujumdar, R Jain, K Saluja - Journal of Electronic Testing, 1994 - Springer
In this article we propose two novel methods to improve the testability of the designs
produced by high-level synthesis tools. Our first method, loop-breaking algorithm, identifies …
produced by high-level synthesis tools. Our first method, loop-breaking algorithm, identifies …
High-level synthesis for testability: A survey and perspective
KD Wagner, S Dey - Proceedings of the 33rd annual Design Automation …, 1996 - dl.acm.org
High-Level Synthesis for Testability: A Survey and Perspective Page 1 High-Level Synthesis for
Testability: A Survey and Perspective Kenneth D. Wagner Synopsys, Inc. 700 East Middlefield …
Testability: A Survey and Perspective Kenneth D. Wagner Synopsys, Inc. 700 East Middlefield …
An improved method for RTL synthesis with testability tradeoffs
H Harmanani, CA Papachristou - Proceedings of 1993 …, 1993 - ieeexplore.ieee.org
A method for high level synthesis with testability is presented with the objective to generate
self-testable RTL datapath structures. We base our approach on a new improved testability …
self-testable RTL datapath structures. We base our approach on a new improved testability …