Multi-ported RAMs are essential for high-performance parallel computation systems. VLIW
and vector processors, CGRAs, DSPs, CMPs and other processing systems often rely upon …

Network topology and routing algorithms stand as pivotal decision points that profoundly
impact the performance of Network-on-Chip (NoC) systems. As core counts rise, so does the …

Multiported RAMs are essential for high-performance parallel computation systems. VLIW
and vector processors, CGRAs, DSPs, CMPs, and other processing systems often rely upon …

In this article, we present a reusable Java processor IP for application processors of
embedded systems. For the Java microarchitecture, we propose a low-cost stack memory …

Interconnect power is the factor that dominates the power consumption on the on-chip
memory architecture. Almost all dedicated wires and buses are replaced with packet …

In this paper, we propose the design of the stack memory for a low-cost Java processor that
explores instruction-level parallelism. The Java virtual machine (JVM) is a stack machine …

In the digital signal processing (DSP) adders have higher precedence. Adders are the basic
blocks of the digital signal processing chips and are of different types. The different types of …

Branch prediction is critical to the instruction-level parallelism. Researchers have been
focusing on branch direction algorithm for a long time and recent improvement on the …

This paper presents an adaptive particle swarm optimization differentially perturbed velocity
(APSO-DV) method for dealing with optimal reactive power dispatch aiming at power loss …

Abstract Network-on-Chip (NoC) architectures offer significant performance improvements
over traditional bus-based systems. However, as NoC designs become more complex …