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A double-tail latch-type voltage sense amplifier with 18ps setup+ hold time
D Schinkel, E Mensink, E Klumperink… - … solid-state circuits …, 2007 - ieeexplore.ieee.org
A latch-type voltage sense amplifier in 90nm CMOS is designed with a separated input and
cross-coupled stage. This separation enables fast operation over a wide common-mode and …
cross-coupled stage. This separation enables fast operation over a wide common-mode and …
A dynamic and differential CMOS logic with signal independent power consumption to withstand differential power analysis on smart cards
To protect security devices such as smart cards against power attacks, we propose a
dynamic and differential CMOS logic style. The logic operates with a power consumption …
dynamic and differential CMOS logic style. The logic operates with a power consumption …
Yield and speed optimization of a latch-type voltage sense amplifier
B Wicht, T Nirschl… - IEEE journal of solid-state …, 2004 - ieeexplore.ieee.org
A quantitative yield analysis of a latch-type voltage sense amplifier with a high-impedance
differential input stage is presented. It investigates the impact of supply voltage, input DC …
differential input stage is presented. It investigates the impact of supply voltage, input DC …
CMOS imager with 1024 SPADs and TDCs for single-photon timing and 3-D time-of-flight
We present a CMOS imager consisting of smart pixels, each one able to detect single
photons in the 300–900 nm wavelength range and to perform both photon-counting and …
photons in the 300–900 nm wavelength range and to perform both photon-counting and …
Sense amplifier based flip-flop
R Ahmadi - US Patent 7,692,466, 2010 - Google Patents
(57) ABSTRACT A circuit includes an input stage, an output stage, and a delay stage. The
input stage is operative to receive a clock signal and a first and second input signal. The …
input stage is operative to receive a clock signal and a first and second input signal. The …
[KÖNYV][B] All-digital frequency synthesizer in deep-submicron CMOS
RB Staszewski, PT Balsara - 2006 - books.google.com
A new and innovative paradigm for RF frequency synthesis and wireless transmitter design
Learn the techniques for designing and implementing an all-digital RF frequency …
Learn the techniques for designing and implementing an all-digital RF frequency …
1.3 V 20 ps time-to-digital converter for frequency synthesis in 90-nm CMOS
RB Staszewski, S Vemulapalli, P Vallur… - … on Circuits and …, 2006 - ieeexplore.ieee.org
We propose and demonstrate a 20-ps time-to-digital converter (TDC) realized in 90-nm
digital CMOS. It is used as a phase/frequency detector and charge pump replacement in an …
digital CMOS. It is used as a phase/frequency detector and charge pump replacement in an …
A 78 dB SNDR 87 mW 20 MHz Bandwidth Continuous-Time ADC With VCO-Based Integrator and Quantizer Implemented in 0.13 m CMOS
M Park, MH Perrott - IEEE Journal of Solid-State Circuits, 2009 - ieeexplore.ieee.org
The use of a VCO-based integrator and quantizer within a continuous-time (CT) ΔΣ analog-
to-digital converter (ADC) structure is explored, and a custom prototype in a 0.13 μm CMOS …
to-digital converter (ADC) structure is explored, and a custom prototype in a 0.13 μm CMOS …
High-performance and low-power conditional discharge flip-flop
P Zhao, TK Darwish… - IEEE transactions on very …, 2004 - ieeexplore.ieee.org
In this paper, high-performance flip-flops are analyzed and classified into two categories: the
conditional precharge and the conditional capture technologies. This classification is based …
conditional precharge and the conditional capture technologies. This classification is based …
A modular, direct time-of-flight depth sensor in 45/65-nm 3-D-stacked CMOS technology
This article introduces a modular, direct time-of-flight (TOF) depth sensor. Each module is
digitally synthesized and features a 2 * (8 * 8) single-photon avalanche diode (SPAD) pixel …
digitally synthesized and features a 2 * (8 * 8) single-photon avalanche diode (SPAD) pixel …