Gate sizing for timing optimization is performed extensively throughout electronic design
automation (EDA) flows. However, increasing design sizes and time-to-market pressure …

Gate sizing is a fundamental netlist optimization move and researchers have used
supervised learning-based models in gate sizers. Recently, Reinforcement Learning (RL) …

Modern electronic design automation flows depend on both implementation and signoff
tools to perform timing-constrained power optimization through Engineering Change Orders …

The objective of a leakage recovery step is to make use of positive slack and reduce power
by performing appropriate standard-cell swaps such as threshold-voltage (Vth) or channel …

Modern high-performance System-on-Chip (SoC) design flows highly depend on signoff
tools to perform timing-constrained power optimization through Engineering Change Orders …

Threshold voltage (V th) assignment is convenient for leakage optimization due to the
exponential relation between leakage power and V th by swap** logic cells without …

Self-supervised learning has shown great promise in leveraging large amounts of unlabeled
data to achieve higher accuracy than supervised learning methods in many domains …

For many years, discrete gate sizing has been widely used for timing and power optimization
in VLSI designs. The importance of gate sizing optimization has been emphasized by …

Modern systems-on-a-chip and microprocessors, eg, those in smart phones and laptops,
typically have multiple operating conditions, such as video streaming, Web browsing …

Engineering change order (ECO) plays an important role in design flow to perform leakage
optimization with gate-sizing and assignment approaches. Unfortunately, it is extremely time …