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Rl-sizer: Vlsi gate sizing for timing optimization using deep reinforcement learning
Gate sizing for timing optimization is performed extensively throughout electronic design
automation (EDA) flows. However, increasing design sizes and time-to-market pressure …
automation (EDA) flows. However, increasing design sizes and time-to-market pressure …
Transsizer: A novel transformer-based fast gate sizer
S Nath, G Pradipta, C Hu, T Yang, B Khailany… - Proceedings of the 41st …, 2022 - dl.acm.org
Gate sizing is a fundamental netlist optimization move and researchers have used
supervised learning-based models in gate sizers. Recently, Reinforcement Learning (RL) …
supervised learning-based models in gate sizers. Recently, Reinforcement Learning (RL) …
Learning-driven physically-aware large-scale circuit gate sizing
Gate sizing plays an important role in timing optimization after physical design. Existing
machine learning-based gate sizing works cannot optimize timing on multiple timing paths …
machine learning-based gate sizing works cannot optimize timing on multiple timing paths …
Dagsizer: A directed graph convolutional network approach to discrete gate sizing of vlsi graphs
The objective of a leakage recovery step is to make use of positive slack and reduce power
by performing appropriate standard-cell swaps such as threshold-voltage (Vth) or channel …
by performing appropriate standard-cell swaps such as threshold-voltage (Vth) or channel …
Eco-gnn: Signoff power prediction using graph neural networks with subgraph approximation
YC Lu, S Nath, S Pentapati, SK Lim - ACM Transactions on Design …, 2023 - dl.acm.org
Modern electronic design automation flows depend on both implementation and signoff
tools to perform timing-constrained power optimization through Engineering Change Orders …
tools to perform timing-constrained power optimization through Engineering Change Orders …
A fast learning-driven signoff power optimization framework
YC Lu, S Nath, SSK Pentapati, SK Lim - Proceedings of the 39th …, 2020 - dl.acm.org
Modern high-performance System-on-Chip (SoC) design flows highly depend on signoff
tools to perform timing-constrained power optimization through Engineering Change Orders …
tools to perform timing-constrained power optimization through Engineering Change Orders …
An efficient leakage power optimization framework based on reinforcement learning with graph neural network
P Cao, Y Dong, Z Zhang, W Ding, J Wang - Scientific Reports, 2024 - nature.com
Threshold voltage (V th) assignment is convenient for leakage optimization due to the
exponential relation between leakage power and V th by swap** logic cells without …
exponential relation between leakage power and V th by swap** logic cells without …
Enhancing sensitivity-based power reduction for an industry IC design context
H Fatemi, AB Kahng, H Lee, J Li, JP de Gyvez - Integration, 2019 - Elsevier
For many years, discrete gate sizing has been widely used for timing and power optimization
in VLSI designs. The importance of gate sizing optimization has been emphasized by …
in VLSI designs. The importance of gate sizing optimization has been emphasized by …
Efficient and accurate eco leakage optimization framework with gnn and bidirectional lstm
P Cao, G He, W Ding, Z Zhang… - IEEE Transactions on …, 2023 - ieeexplore.ieee.org
Engineering change order (ECO) plays an important role in design flow to perform leakage
optimization with gate-sizing and assignment approaches. Unfortunately, it is extremely time …
optimization with gate-sizing and assignment approaches. Unfortunately, it is extremely time …
GRA-LPO: Graph convolution based leakage power optimization
U Mallappa, CK Cheng - Proceedings of the 26th Asia and South Pacific …, 2021 - dl.acm.org
Static power consumption is a critical challenge for IC designs, particularly for mobile and
IoT applications. A final post-layout step in modern design flows involves a leakage recovery …
IoT applications. A final post-layout step in modern design flows involves a leakage recovery …