[BOOK][B] Electronic design automation: synthesis, verification, and test
This book provides broad and comprehensive coverage of the entire EDA flow. EDA/VLSI
practitioners and researchers in need of fluency in an" adjacent" field will find this an …
practitioners and researchers in need of fluency in an" adjacent" field will find this an …
Survey of machine learning for electronic design automation
An increase in demand for semiconductor ICs, recent advancements in machine learning,
and the slowing down of Moore's law have all contributed to the increased interest in using …
and the slowing down of Moore's law have all contributed to the increased interest in using …
A summary-attainment-surface plotting method for visualizing the performance of stochastic multiobjective optimizers
J Knowles - 5th International Conference on Intelligent Systems …, 2005 - ieeexplore.ieee.org
When evaluating the performance of a stochastic optimizer it is sometimes desirable to
express performance in terms of the quality attained in a certain fraction of sample runs. For …
express performance in terms of the quality attained in a certain fraction of sample runs. For …
UST/DME: a clock tree router for general skew constraints
CWA Tsao, CK Koh - ACM Transactions on Design Automation of …, 2002 - dl.acm.org
In this article, we propose new approaches for solving the useful-skew tree (UST) routing
problem [** and Dai 1997]: clock routing subject to general skew constraints. The clock …
problem [** and Dai 1997]: clock routing subject to general skew constraints. The clock …
Advanced Reinforcement Learning Solution for Clock Skew Engineering: Modified Q-Table Update Technique for Peak Current and IR Drop Minimization
This paper discloses a Reinforcement Learning (RL) solution implemented to decrease the
peak current by alteration of the clock skews. Clock skews are elements of the clock network …
peak current by alteration of the clock skews. Clock skews are elements of the clock network …
di/dt Noise in CMOS Integrated Circuits
P Larsson - Analog Design Issues in Digital VLSI Circuits and …, 1997 - Springer
This is an overview paper presenting di/dt noise from a designer's perspective. Analysis and
circuit design techniques are presented taking package parasitics into account. The main …
circuit design techniques are presented taking package parasitics into account. The main …
Timing analysis and optimization of sequential circuits
OFS CIRCUITS - 1999 - Springer
While a decade ago, most books related to integrated circuits began with the phrase," With
the increasing complexity of VLSI circuits...," the new and trendy catch-phrase today is" deep …
the increasing complexity of VLSI circuits...," the new and trendy catch-phrase today is" deep …
IR-ATA: IR annotated timing analysis, a flow for closing the loop between PDN design, IR analysis & timing closure
This paper presents IR-ATA, a novel flow for modeling the timing impact of IR drop during
the physical design and timing closure of an ASIC chip. We first illustrate how the current …
the physical design and timing closure of an ASIC chip. We first illustrate how the current …
A power delivery network and cell placement aware IR-drop mitigation technique: Harvesting unused timing slacks to schedule useful skews
This paper, presents a novel technique for reducing the intensity of IR hot-spots by
leveraging the unused timing slacks to schedule useful skews. The peak current …
leveraging the unused timing slacks to schedule useful skews. The peak current …
Methodology and experimental verification for substrate noise reduction in CMOS mixed-signal ICs with synchronous digital circuits
This paper describes substrate noise reduction techniques for synchronous CMOS circuits.
Low-noise digital design techniques have been implemented and measured on a mixed …
Low-noise digital design techniques have been implemented and measured on a mixed …