A 3-D TCAD framework for NBTI—Part I: Implementation details and FinFET channel material impact

R Tiwari, N Parihar, K Thakor, HY Wong… - … on Electron Devices, 2019 - ieeexplore.ieee.org
The time kinetics of interface trap generation and passivation (ΔN IT) and its contribution (ΔV
IT) during and after negative bias temperature instability (NBTI) stress is calculated by using …

Integrated modeling of self-heating of confined geometry (FinFET, NWFET, and NSHFET) transistors and its implications for the reliability of sub-20 nm modern …

W Ahn, SH Shin, C Jiang, H Jiang, MA Wahab… - Microelectronics …, 2018 - Elsevier
The evolution of transistor topology from planar to confined geometry transistors (ie, FinFET,
Nanowire FET, Nanosheet FET) has met the desired performance specification of sub-20 nm …

Comparative characterization of NWFET and FinFET transistor structures using TCAD modeling

KO Petrosyants, DS Silkin, DA Popov - Micromachines, 2022 - mdpi.com
A complete comparison for 14 nm FinFET and NWFET with stacked nanowires was carried
out. The electrical and thermal performances in two device structures were analyzed based …

New insight into negative bias temperature instability degradation during self-heating in nanoscale bulk FinFETs

D Son, K Hong, H Shim, S Pae… - IEEE Electron Device …, 2019 - ieeexplore.ieee.org
In this letter, we investigate the threshold voltage shift (ΔV th) by negative bias temperature
instability (NBTI) coupled with the self-heating effect (SHE) in a 14-nm bulk p-FinFET. To …

Impact of self-heating on performance and reliability in FinFET and GAAFET designs

VA Chhabria, SS Sapatnekar - 20th International Symposium …, 2019 - ieeexplore.ieee.org
Modern transistors such as FinFETs and gate-all-around FETs (GAAFETs) suffer from
excessive heat confinement due to their small size and three-dimensional geometries, with …

A predictive model for IC self-heating based on effective medium and image charge theories and its implications for interconnect and transistor reliability

W Ahn, H Zhang, T Shen, C Christiansen… - … on Electron Devices, 2017 - ieeexplore.ieee.org
Spatially resolved precise prediction of local temperature T (x, y, z) is essential to evaluate
Arrhenius-activated interconnect (eg, electromigration) and transistor reliability (eg, NBTI …

Modeling channel length scaling impact on NBTI in RMG Si p-FinFETs

N Parihar, R Tiwari, S Mahapatra - … International Conference on …, 2018 - ieeexplore.ieee.org
Negative Bias Temperature Instability (NBTI) stress and recovery time kinetics from
Replacement Metal Gate (RMG) High-K Metal Gate (HKMG) p-channel FinFETs are …

Modeling of process (Ge, N) dependence and mechanical strain impact on NBTI in HKMG SiGe GF FDSOI p-MOSFETs and RMG p-FinFETs

N Parihar, R Tiwari, C Ndiaye, M Arabi… - … on Simulation of …, 2018 - ieeexplore.ieee.org
A physical framework is used to model time kinetics of Negative Bias Temperature Instability
(NBTI) in Si and SiGe FDSOI p-MOSFETs and p-FinFETs. The effects of Germanium (Ge%) …

Predictive TCAD for NBTI stress-recovery in various device architectures and channel materials

S Mishra, HY Wong, R Tiwari… - 2017 IEEE …, 2017 - ieeexplore.ieee.org
A 3-D TCAD framework is proposed for simulating Negative Bias Temperature Instability
(NBTI) in Silicon (Si) and Silicon Germanium (SiGe) channel p-MOSFETs. Different types of …

Aggravated NBTI reliability due to hard-to-detect open defects

G Aguirre, J Gamez, V Champac - Microelectronics Reliability, 2024 - Elsevier
FinFET technology has become an attractive candidate for high-performance and power-
efficient applications. In the other hand, the behavior of FinFET devices is influenced by self …