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Minimizing WCET for real-time embedded systems via static instruction cache locking
Cache is effective in bridging the gap between processor and memory speed. It is also a
source of unpredictability because of its dynamic and adaptive behavior. Worst-case …
source of unpredictability because of its dynamic and adaptive behavior. Worst-case …
WCET-centric partial instruction cache locking
Caches play an important role in embedded systems by bridging the performance gap
between high speed processors and slow memory. At the same time, caches introduce …
between high speed processors and slow memory. At the same time, caches introduce …
Task assignment with cache partitioning and locking for wcet minimization on mpsoc
Cache is known for its unpredictability in embedded systems. Cache locking technique is
often utilized to guarantee a tighter prediction of Worst-Case Execution Time (WCET) which …
often utilized to guarantee a tighter prediction of Worst-Case Execution Time (WCET) which …
WCET-driven cache-aware code positioning
Code positioning is a well-known compiler optimization aiming at the improvement of the
instruction cache behavior. A contiguous map** of code fragments in memory avoids …
instruction cache behavior. A contiguous map** of code fragments in memory avoids …
Optimal task placement to improve cache performance
G Gebhard, S Altmeyer - Proceedings of the 7th ACM & IEEE …, 2007 - dl.acm.org
Most recent embedded systems use caches to improve their average performance. Current
timing analyses are able to compute safe timing guarantees for these systems, if tasks are …
timing analyses are able to compute safe timing guarantees for these systems, if tasks are …
Instruction cache locking for multi-task real-time embedded systems
In a multi-task embedded system, a cache is shared by different tasks, which increases the
complexity of cache management and the unpredictability of cache behavior. This …
complexity of cache management and the unpredictability of cache behavior. This …
Automatic code overlay generation and partially redundant code fetch elimination
There is an increasing interest in explicitly managed memory hierarchies, where a hierarchy
of distinct memories is exposed to the programmer and managed explicitly in software …
of distinct memories is exposed to the programmer and managed explicitly in software …
Instruction cache locking for embedded systems using probability profile
Cache is effective in bridging the gap between processor and memory speed. It is also a
source of unpredictability because of its dynamic and adaptive behavior. A lot of modern …
source of unpredictability because of its dynamic and adaptive behavior. A lot of modern …