Minimizing WCET for real-time embedded systems via static instruction cache locking

T Liu, M Li, CJ Xue - 2009 15th IEEE Real-Time and …, 2009 - ieeexplore.ieee.org
Cache is effective in bridging the gap between processor and memory speed. It is also a
source of unpredictability because of its dynamic and adaptive behavior. Worst-case …

WCET-centric partial instruction cache locking

H Ding, Y Liang, T Mitra - Proceedings of the 49th Annual Design …, 2012 - dl.acm.org
Caches play an important role in embedded systems by bridging the performance gap
between high speed processors and slow memory. At the same time, caches introduce …

Task assignment with cache partitioning and locking for wcet minimization on mpsoc

T Liu, Y Zhao, M Li, CJ Xue - 2010 39th International …, 2010 - ieeexplore.ieee.org
Cache is known for its unpredictability in embedded systems. Cache locking technique is
often utilized to guarantee a tighter prediction of Worst-Case Execution Time (WCET) which …

WCET-driven cache-aware code positioning

H Falk, H Kotthaus - Proceedings of the 14th international conference on …, 2011 - dl.acm.org
Code positioning is a well-known compiler optimization aiming at the improvement of the
instruction cache behavior. A contiguous map** of code fragments in memory avoids …

Optimal task placement to improve cache performance

G Gebhard, S Altmeyer - Proceedings of the 7th ACM & IEEE …, 2007 - dl.acm.org
Most recent embedded systems use caches to improve their average performance. Current
timing analyses are able to compute safe timing guarantees for these systems, if tasks are …

Instruction cache locking for multi-task real-time embedded systems

T Liu, M Li, CJ Xue - Real-Time Systems, 2012 - Springer
In a multi-task embedded system, a cache is shared by different tasks, which increases the
complexity of cache management and the unpredictability of cache behavior. This …

Automatic code overlay generation and partially redundant code fetch elimination

C Jang, J Lee, B Egger, S Ryu - ACM Transactions on Architecture and …, 2012 - dl.acm.org
There is an increasing interest in explicitly managed memory hierarchies, where a hierarchy
of distinct memories is exposed to the programmer and managed explicitly in software …

Instruction cache locking for embedded systems using probability profile

T Liu, M Li, CJ Xue - Journal of Signal Processing Systems, 2012 - Springer
Cache is effective in bridging the gap between processor and memory speed. It is also a
source of unpredictability because of its dynamic and adaptive behavior. A lot of modern …