Synthesis and applications of III–V nanowires

E Barrigón, M Heurlin, Z Bi, B Monemar… - Chemical …, 2019 - ACS Publications
Low-dimensional semiconductor materials structures, where nanowires are needle-like one-
dimensional examples, have developed into one of the most intensely studied fields of …

[HTML][HTML] State of the art and future perspectives in advanced CMOS technology

HH Radamson, H Zhu, Z Wu, X He, H Lin, J Liu… - Nanomaterials, 2020 - mdpi.com
The international technology roadmap of semiconductors (ITRS) is approaching the
historical end point and we observe that the semiconductor industry is driving …

How to control defect formation in monolithic III/V hetero-epitaxy on (100) Si? A critical review on current approaches

B Kunert, Y Mols, M Baryshniskova… - Semiconductor …, 2018 - iopscience.iop.org
The monolithic hetero-integration of III/V materials on Si substrates could enable a multitude
of new device applications and functionalities which would benefit from both the excellent …

Nanowire & nanosheet FETs for ultra-scaled, high-density logic and memory applications

A Veloso, T Huynh-Bao, P Matagne, D Jang… - Solid-State …, 2020 - Elsevier
We report on vertically stacked lateral nanowires (NW)/nanosheets (NS) gate-all-around
(GAA) FET devices as promising candidates to obtain a better power-performance metric for …

Nanometer-Scale III-V MOSFETs

JA Del Alamo, DA Antoniadis, J Lin… - IEEE Journal of the …, 2016 - ieeexplore.ieee.org
After 50 years of Moore's Law, Si CMOS, the mainstream logic technology, is on a course of
diminishing returns. The use of new semiconductor channel materials with improved …

High-mobility GaSb nanostructures cointegrated with InAs on Si

M Borg, H Schmid, J Gooth, MD Rossell, D Cutaia… - ACS …, 2017 - ACS Publications
GaSb nanostructures integrated on Si substrates are of high interest for p-type transistors
and mid-IR photodetectors. Here, we investigate the metalorganic chemical vapor …

Integration of III/V hetero-structures by selective area growth on Si for nano-and optoelectronics

B Kunert, W Guo, Y Mols, R Langer, K Barla - Ecs Transactions, 2016 - iopscience.iop.org
Selective area growth by metal organic vapor phase epitaxy of III/V nano ridges on patterned
(001) Si substrates was investigated applying different growth conditions. The deposition of …

III-V/Ge MOS device technologies for low power integrated systems

S Takagi, M Noguchi, M Kim, SH Kim, CY Chang… - Solid-State …, 2016 - Elsevier
CMOS utilizing high mobility III-V/Ge channels on Si substrates is expected to be one of the
promising devices for high performance and low power integrated systems in the future …

Junctionless versus inversion-mode lateral semiconductor nanowire transistors

A Veloso, P Matagne, E Simoen, B Kaczer… - Journal of Physics …, 2018 - iopscience.iop.org
This paper reports on gate-all-around silicon nanowire field-effect transistors (FETs) built in
a lateral configuration, which represent the ultimate scaling limit of triple-gate finFET devices …

Electrical Characteristics of In0.53Ga0.47As Gate-All-Around MOSFETs With Different Nanowire Shapes

HL Ko, QH Luc, P Huang, SM Chen… - … on Electron Devices, 2022 - ieeexplore.ieee.org
In this article, we investigate the electrical properties of In 0.53 Ga 0.47 As gate-all-around
(GAA) MOSFETs with different nanowire shapes. InGaAs GAA MOSFETs with trapezoid and …