HotSpot: A compact thermal modeling methodology for early-stage VLSI design

W Huang, S Ghosh, S Velusamy… - … Transactions on very …, 2006 - ieeexplore.ieee.org
This paper presents HotSpot-a modeling methodology for develo** compact thermal
models based on the popular stacked-layer packaging scheme in modern very large-scale …

Destination prediction by sub-trajectory synthesis and privacy protection against such prediction

AY Xue, R Zhang, Y Zheng, X **e… - 2013 IEEE 29th …, 2013 - ieeexplore.ieee.org
Destination prediction is an essential task for many emerging location based applications
such as recommending sightseeing places and targeted advertising based on destination. A …

Thermal modeling, analysis, and management in VLSI circuits: Principles and methods

M Pedram, S Nazarian - Proceedings of the IEEE, 2006 - ieeexplore.ieee.org
The growing packing density and power consumption of very large scale integration (VLSI)
circuits have made thermal effects one of the most important concerns of VLSI designers …

3D-ICE: Fast compact transient thermal modeling for 3D ICs with inter-tier liquid cooling

A Sridhar, A Vincenzi, M Ruggiero… - 2010 IEEE/ACM …, 2010 - ieeexplore.ieee.org
Three dimensional stacked integrated circuits (3D ICs) are extremely attractive for
overcoming the barriers in interconnect scaling, offering an opportunity to continue the …

3D facial expression recognition based on primitive surface feature distribution

J Wang, L Yin, X Wei, Y Sun - 2006 IEEE Computer Society …, 2006 - ieeexplore.ieee.org
The creation of facial range models by 3D imaging systems has led to extensive work on 3D
face recognition [19]. However, little work has been done to study the usefulness of such …

Parameter variation tolerance and error resiliency: New design paradigm for the nanoscale era

S Ghosh, K Roy - Proceedings of the IEEE, 2010 - ieeexplore.ieee.org
Variations in process parameters affect the operation of integrated circuits (ICs) and pose a
significant threat to the continued scaling of transistor dimensions. Such parameter …

3-D thermal-ADI: A linear-time chip level transient thermal simulator

TY Wang, CCP Chen - … on computer-aided design of integrated …, 2002 - ieeexplore.ieee.org
Recent study shows that the nonuniform thermal distribution not only has an impact on the
substrate but also interconnects. Hence, three-dimensional (3-D) thermal analysis is crucial …

A survey of chip-level thermal simulators

H Sultan, A Chauhan, SR Sarangi - ACM Computing Surveys (CSUR), 2019 - dl.acm.org
Thermal modeling and simulation have become imperative in recent years owing to the
increased power density of high performance microprocessors. Temperature is a first-order …

Modeling and analysis of nonuniform substrate temperature effects on global ULSI interconnects

AH Ajami, K Banerjee, M Pedram - IEEE Transactions on …, 2005 - ieeexplore.ieee.org
Nonuniform thermal profiles on the substrate in high-performance ICs can significantly
impact the performance of global on-chip interconnects. This paper presents a detailed …

Cell-level placement for improving substrate thermal distribution

CH Tsai, SM Kang - … Transactions on Computer-aided design of …, 2000 - ieeexplore.ieee.org
The dramatic increase of power consumption in very large scale integration circuits has led
to high operating temperature and large thermal gradient, thereby resulting in serious timing …