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FPGA HLS today: successes, challenges, and opportunities
The year 2011 marked an important transition for FPGA high-level synthesis (HLS), as it
went from prototy** to deployment. A decade later, in this article, we assess the progress …
went from prototy** to deployment. A decade later, in this article, we assess the progress …
An overview of efficient interconnection networks for deep neural network accelerators
Deep Neural Networks (DNNs) have shown significant advantages in many domains, such
as pattern recognition, prediction, and control optimization. The edge computing demand in …
as pattern recognition, prediction, and control optimization. The edge computing demand in …
Detecting backdoors during the inference stage based on corruption robustness consistency
Deep neural networks are proven to be vulnerable to backdoor attacks. Detecting the trigger
samples during the inference stage, ie, the test-time trigger sample detection, can prevent …
samples during the inference stage, ie, the test-time trigger sample detection, can prevent …
Confuciux: Autonomous hardware resource assignment for dnn accelerators using reinforcement learning
DNN accelerators provide efficiency by leveraging reuse of activations/weights/outputs
during the DNN computations to reduce data movement from DRAM to the chip. The reuse is …
during the DNN computations to reduce data movement from DRAM to the chip. The reuse is …
Scalehls: A new scalable high-level synthesis framework on multi-level intermediate representation
High-level synthesis (HLS) has been widely adopted as it significantly improves the
hardware design productivity and enables efficient design space exploration (DSE). Existing …
hardware design productivity and enables efficient design space exploration (DSE). Existing …
ThunderGP: HLS-based graph processing framework on FPGAs
FPGA has been an emerging computing infrastructure in datacenters benefiting from
features of fine-grained parallelism, energy efficiency, and reconfigurability. Meanwhile …
features of fine-grained parallelism, energy efficiency, and reconfigurability. Meanwhile …
Aeva: Black-box backdoor detection using adversarial extreme value analysis
DNNExplorer: a framework for modeling and exploring a novel paradigm of FPGA-based DNN accelerator
Existing FPGA-based DNN accelerators typically fall into two design paradigms. Either they
adopt a generic reusable architecture to support different DNN networks but leave some …
adopt a generic reusable architecture to support different DNN networks but leave some …