This paper describes a delay insertion method that improves the efficiency of clock skew
scheduling. Clock skew scheduling is performed on synchronous circuits in order to improve …

We present a design methodology for synchronous single-rail domino logic circuits, where
inverting and nonmonotonic logic functions can be integrated into a pipeline with almost …

Power Supply Noise (PSN) may be induced by environmental or operational conditions, and
has impact on digital systems performance. Field Programmable Gate Array (FPGA) vendors …

In high performance designs, dynamic circuits, such as domino logic, are used because of
their high speed. However, due to its low noise margin, domino circuits do not scale …

This paper presents new circuit configurations for a more robust and efficient form of self-
resetting CMOS (SRCMOS). Prior structures for SRCMOS have very high performance but …

In nanometer technologies, as variability is becoming one of the leading causes for chip
failures, signal integrity is a key issue for high-performance digital System-on-Chip (SoC) …

This paper addresses the effects of time borrowing and clock skew scheduling on level-
sensitive synchronous circuits. Synchronization of level-sensitive circuits can be …

The implementation of complex functionality in low-power nano-CMOS technologies leads
to enhance susceptibility to parametric disturbances (environmental, and operation …

A new methodology is proposed to increase the robustness of pipeline-based circuits. The
goal is to improve signal integrity in the presence of power-supply voltage (V DD) and/or …

The implementation of complex, high-performance functionalities in low-power nano-CMOS
technologies faces significant design and test challenges related to the increased …