HIDA: A Hierarchical Dataflow Compiler for High-Level Synthesis
Dataflow architectures are growing in popularity due to their potential to mitigate the
challenges posed by the memory wall inherent to the Von Neumann architecture. At the …
challenges posed by the memory wall inherent to the Von Neumann architecture. At the …
PASTA: Programming and Automation Support for Scalable Task-Parallel HLS Programs on Modern Multi-Die FPGAs
In recent years, there has been increasing adoption of FPGAs in datacenters as hardware
accelerators, where a large population of end users are software developers. While high …
accelerators, where a large population of end users are software developers. While high …
Callipepla: Stream centric instruction set and mixed precision for accelerating conjugate gradient solver
The continued growth in the processing power of FPGAs coupled with high bandwidth
memories (HBM), makes systems like the **linx U280 credible platforms for linear solvers …
memories (HBM), makes systems like the **linx U280 credible platforms for linear solvers …
SpectraFlux: Harnessing the Flow of Multi-FPGA in Mass Spectrometry Clustering
The identification and quantification of proteins through mass spectrometry (MS) are
foundational to proteomics, offering insights into biological systems and disease states …
foundational to proteomics, offering insights into biological systems and disease states …
Lightning Talk: The Next Wave of High-level Synthesis
D Chen - 2023 60th ACM/IEEE Design Automation Conference …, 2023 - ieeexplore.ieee.org
Recent works established new High-Level Synthesis (HLS) solutions translating AI models
described in PyTorch to customized AI accelerators automatically. By adopting PyTorch as …
described in PyTorch to customized AI accelerators automatically. By adopting PyTorch as …
LevelST: Stream-based Accelerator for Sparse Triangular Solver
Over the past decade, much progress has been made to advance the acceleration of sparse
linear operators such as SpMM and SpMV on FPGAs. Nevertheless, few works have …
linear operators such as SpMM and SpMV on FPGAs. Nevertheless, few works have …
HMT: Hierarchical Memory Transformer for Long Context Language Processing
Transformer-based large language models (LLM) have been widely used in language
processing applications. However, most of them restrict the context window that permits the …
processing applications. However, most of them restrict the context window that permits the …
Hihispmv: Sparse matrix vector multiplication with hierarchical row reductions on fpgas with high bandwidth memory
The multiplication of a sparse matrix with a dense vector is a vital operation in linear algebra,
with applications in numerous contexts. After earlier research on FPGA acceleration of this …
with applications in numerous contexts. After earlier research on FPGA acceleration of this …
Partitioning Large-Scale, Multi-FPGA Applications for the Data Center
With the deployment of FPGAs in a data center, there is the opportunity to build large multi-
FPGA applications. In this paper, we design a partitioner to address the problem of efficiently …
FPGA applications. In this paper, we design a partitioner to address the problem of efficiently …
[PDF][PDF] Latency Insensitivity Testing for Dataflow HLS Designs
Dataflow high-level synthesis (HLS) tools automatically map a high-level software program
to a dataflow hardware design. When testing the design, the HLS tool takes a testing …
to a dataflow hardware design. When testing the design, the HLS tool takes a testing …