Field Programmable Gate Arrays (FPGAs) are spatial architectures with a heterogeneous
reconfigurable fabric. They are state-of-the-art for prototy**, telecommunications …

This paper introduces Tiramisu, a polyhedral framework designed to generate high
performance code for multiple platforms including multicores, GPUs, and distributed …

The ubiquity of accelerators in high-performance computing has driven programming
complexity beyond the skill-set of the average domain scientist. To maintain performance …

The generation of custom hardware accelerators for applications implemented within high-
level productive programming frameworks requires considerable manual effort. To automate …

Field programmable gate arrays (FPGAs) excel in low power and high throughput
computations, but they are challenging to program. Traditionally, developers rely on …

Heterogeneous computing systems with tightly coupled processors and reconfigurable logic
blocks provide great scope to improve software performance by executing each section of …

This paper addresses the need for automatic and efficient generation of host driver code for
arbitrary custom AXI-based accelerators targeting linear algebra algorithms, an important …

Domain-specific accelerators obtain performance benefits by restricting their algorithmic
domain. These accelerators utilize specialized languages constrained to particular …

This paper aims at high and portable performance for tensor computations across spatial
(eg, FPGAs) and vector architectures (eg, GPUs). The state-of-the-art usually address …

FPGAs have found their way into data centers as accelerator cards, making reconfigurable
computing more accessible for high-performance applications. At the same time, new high …