Computer architects employ a series of performance optimizations at the micro-architecture
level. These optimizations are meant to be invisible to the programmer but they are implicitly …

Nonvolatile memory (NVM) technologies have gained increasing attention thanks to their
density and durability benefits. However, leveraging NVM can cause a crash consistency …

This paper presents NoSQ (short for No Store Queue), a microarchitecture that performs
store-load communication without a store queue and without executing stores in the outof …

Modern processors use CAM-based load and store queues (LQ/SQ) to support out-of-order
memory scheduling and store-to-load forwarding. However, the LQ and SQ scale poorly for …

The speed gap between processor and memory continues to limit performance. To address
this problem, we explore the potential of eliminating zero loads-loads accessing memory …

Conventional load/store queues (LSQs) are an impediment to both power-efficient execution
in superscalar processors and scaling tolarge-window designs. In this paper, we propose …

Research shows that, under certain circumstances, people using GSS can be substantially
more productive than people who do not. However GSS has been slow to transition into the …

In a processor, a disambiguation-free out of order load store queue method. The method
includes implementing a memory resource that can be accessed by a plurality of …

A store operation is called “silent” if it writes in memory a value that is already there. The
ability to detect silent stores is important, because they might indicate performance bugs …

ARM Memory Tagging Extension (MTE) is a new hardware feature introduced in ARMv8. 5-
A architecture, aiming to detect memory corruption vulnerabilities. The low overhead of MTE …