Robustness analysis of 3–2 adder compressor designed in 7-nm FinFET technology

G Andrade, M Silva, C Schneider… - … on Circuits and …, 2023 - ieeexplore.ieee.org
Adder compressors (ACs) have been employed for several prominent computing datapaths
as multipliers, machine learning, discrete transforms, and filters. This brief investigates the …

Design of a low power and robust VLSI power line interference canceler with optimized arithmetic operators

MMA Da Rosa, PÜ da Costa, EAC da Costa… - … Integrated Circuits and …, 2022 - Springer
The electric generator's functional performance suffers from harmonic distortions such as
first, second, and third-order. This work proposes a low power dissipation VLSI hardware …

Energy-efficient Hadamard-based SATD hardware architectures through calculation reuse

I Seidel, M Monteiro, B Bonotto… - … on Circuits and …, 2019 - ieeexplore.ieee.org
The Hadamard-based Sum of Absolute Transformed Differences (SATD) is a distortion
metric that correlates better with other video encoding steps than the commonly used Sum of …

SAD or SATD? how the distortion metric impacts a Fractional Motion Estimation VLSI architecture

I Seidel, V Rodrigues Filho, M Grellert… - 2021 IEEE 23rd …, 2021 - ieeexplore.ieee.org
Video coding systems have to deal with a number of tradeoffs. The decision of adopting a
specific distortion metric in the Fractional Motion Estimation (FME) step, for instance …

An efficient N-bit 8-2 adder compressor with a constant internal carry propagation delay

TV Fontanari, G Paim, LMG Rocha… - 2020 IEEE 11th Latin …, 2020 - ieeexplore.ieee.org
Adder compressors (AC) have been extensively used in digital circuits like multipliers and
transforms where several multi-bit operands have to be summed in parallel. Most available …

Approximate SATD hardware accelerator using the 8× 8 Hadamard transform

MF Stigger, VHS Lima, LB Soares… - 2020 IEEE 11th Latin …, 2020 - ieeexplore.ieee.org
Sum of Absolute Transformed Differences (SATD) is a distortion metric based on the
Hadamard Transform. It is used in current video encoders inside the refinement stage of …

A fast monolithic 8-2 adder compressor circuit

T Fontanari, G Paim, LMG Rocha, GM Santana… - Journal of Integrated …, 2019 - jics.org.br
Adder compressor architectures have been widely used in multipliers and have recently
achieved improvements over conventional approaches in the computation of multiple …

The 4-2 Fused Adder–Subtractor Compressor for Low-Power Butterfly-Based Hardware Architectures

B Silveira, G Paim, BA Abreu… - Circuits, Systems, and …, 2022 - Springer
Over the years, the use of adder compressors has been a promising alternative to reduce
power of dedicated hardware architectures. Adder compressors are able to perform several …

Configurable approximate hardware accelerator to compute SATD and SAD metrics for low power all-intra high efficiency video coding

VHS Lima, MF Stigger, LB Soares… - 2021 34th SBC …, 2021 - ieeexplore.ieee.org
Connecting billions of network cameras to the cloud is a challenge that heavily taxes the
network bandwidth for video transmissions. High Efficiency Video Coding (HEVC) standard …

High-level synthesis implementation of transform-exempted satd architectures for low-power video coding

T Partanen, A Lemmetti, P Sjövall… - 2021 IEEE International …, 2021 - ieeexplore.ieee.org
This paper presents the first known high-level synthesis (HLS) implementation for the Sum of
Absolute Transformed Differences (SATD) calculation. The proposed hardware architecture …