[SÁCH][B] Memory systems: cache, DRAM, disk

B Jacob, D Wang, S Ng - 2010 - books.google.com
Is your memory hierarchy stop** your microprocessor from performing at the high level it
should be? Memory Systems: Cache, DRAM, Disk shows you how to resolve this problem …

Optimizing NUCA organizations and wiring alternatives for large caches with CACTI 6.0

N Muralimanohar, R Balasubramonian… - 40th Annual IEEE …, 2007 - ieeexplore.ieee.org
A significant part of future microprocessor real estate will be dedicated to 12 or 13 caches.
These on-chip caches will heavily impact processor performance, power dissipation, and …

[PDF][PDF] CACTI 5.1

S Thoziyoor, N Muralimanohar, JH Ahn, NP Jouppi - 2008 - shiftleft.com
CACTI 5.1 is a version of CACTI 5 fixing a number of small bugs in CACTI 5.0. CACTI 5 is
the latest major revision of the CACTI tool for modeling the dynamic power, access time …

Eddie: Em-based detection of deviations in program execution

A Nazari, N Sehatbakhsh, M Alam, A Zajic… - Proceedings of the 44th …, 2017 - dl.acm.org
This paper describes EM-Based Detection of Deviations in Program Execution (EDDIE), a
new method for detecting anomalies in program execution, such as malware and other code …

Organizing the last line of defense before hitting the memory wall for CMPs

C Liu, A Sivasubramaniam… - … Symposium on High …, 2004 - ieeexplore.ieee.org
The last line of defense in the cache hierarchy before going to off-chip memory is very critical
in chip multiprocessors (CMPs) from both the performance and power perspectives. We …

Spectral profiling: Observer-effect-free profiling by monitoring EM emanations

N Sehatbakhsh, A Nazari, A Zajic… - 2016 49th Annual …, 2016 - ieeexplore.ieee.org
This paper presents Spectral Profiling, a new method for profiling program execution without
instrumenting or otherwise affecting the profiled system. Spectral Profiling monitors EM …

A self-tuning cache architecture for embedded systems

C Zhang, F Vahid, R Lysecky - ACM Transactions on Embedded …, 2004 - dl.acm.org
Memory accesses often account for about half of a microprocessor system's power
consumption. Customizing a microprocessor cache's total size, line size, and associativity to …

[SÁCH][B] Embedded Systems Handbook 2-Volume Set

R Zurawski - 2018 - taylorfrancis.com
During the past few years there has been an dramatic upsurge in research and
development, implementations of new technologies, and deployments of actual solutions …

APOGEE: Adaptive prefetching on GPUs for energy efficiency

A Sethia, G Dasika, M Samadi… - Proceedings of the 22nd …, 2013 - ieeexplore.ieee.org
Modern graphics processing units (GPUs) combine large amounts of parallel hardware with
fast context switching among thousands of active threads to achieve high performance …

A way-halting cache for low-energy high-performance systems

C Zhang, F Vahid, J Yang, W Najjar - ACM Transactions on Architecture …, 2005 - dl.acm.org
Caches contribute to much of a microprocessor system's power and energy consumption.
Numerous new cache architectures, such as phased, pseudo-set-associative, way …