Development and challenges of reliability modeling from transistors to circuits
X Yang, Q Sang, C Wang, M Yu… - IEEE Journal of the …, 2023 - ieeexplore.ieee.org
The integration density of electronic systems is limited by the reliability of the integrated
circuits. To guarantee the overall performance, the integrated circuit reliability must be …
circuits. To guarantee the overall performance, the integrated circuit reliability must be …
SRAM stability analysis for different cache configurations due to bias temperature instability and hot carrier injection
Bias Temperature Instability (BTI) and Hot Carrier Injections (HCI) are two of the main effects
that increase a transistor's threshold voltage and further cause performance degradations …
that increase a transistor's threshold voltage and further cause performance degradations …
Remaining useful life prediction in embedded systems using an online auto-updated machine learning based modeling
Abstract Systems on Chips are increasingly involved in critical equipment in the fields of
aeronautics, transportations, and energy. Therefore, monitoring their life cycle is a crucial …
aeronautics, transportations, and energy. Therefore, monitoring their life cycle is a crucial …
A comprehensive time-dependent dielectric breakdown lifetime simulator for both traditional CMOS and FinFET technology
This paper presents techniques for gate-oxide and middle-of-line (MOL) time-dependent
dielectric breakdown (TDDB) lifetime assessment of microprocessors and digital circuits …
dielectric breakdown (TDDB) lifetime assessment of microprocessors and digital circuits …
Comprehensive reliability-aware statistical timing analysis using a unified gate-delay model for microprocessors
A framework is proposed to perform timing analysis of state-of-art microprocessors
considering the impact of process-voltage-temperature (PVT) variations and the aging effect …
considering the impact of process-voltage-temperature (PVT) variations and the aging effect …
Microprocessor aging analysis and reliability modeling due to back-end wearout mechanisms
Back-end wearout mechanisms are major reliability concerns for modern microprocessors.
In this paper, a framework that contains modules for back-end time-dependent dielectric …
In this paper, a framework that contains modules for back-end time-dependent dielectric …
System-level variation-aware aging simulator using a unified novel gate-delay model for bias temperature instability, hot carrier injection, and gate oxide breakdown
A framework is proposed to analyze system-level reliability and evaluate the lifetimes of
state-of-art microprocessors considering the impact of process–voltage–temperature (PVT) …
state-of-art microprocessors considering the impact of process–voltage–temperature (PVT) …
System-level modeling of microprocessor reliability degradation due to bias temperature instability and hot carrier injection
Negative bias temperature instability (NBTI), positive bias temperature instability (PBTI), and
hot carrier injection (HCI) are leading reliability concerns for modern microprocessors. In this …
hot carrier injection (HCI) are leading reliability concerns for modern microprocessors. In this …
Comprehensive reliability and aging analysis on SRAMs within microprocessor systems
A framework is proposed to analyze the impact of both Front End of the Line (FEOL) and
Back End of the Line (BEOL) wearout mechanisms on memories embedded within state-of …
Back End of the Line (BEOL) wearout mechanisms on memories embedded within state-of …
Memory and logic lifetime simulation systems and methods
Aspects of the disclosed technology include a method including extracting, by a processor, a
plurality of features from one from among a layout of a circuit, a netlist of the circuit, and the …
plurality of features from one from among a layout of a circuit, a netlist of the circuit, and the …