Development and challenges of reliability modeling from transistors to circuits

X Yang, Q Sang, C Wang, M Yu… - IEEE Journal of the …, 2023 - ieeexplore.ieee.org
The integration density of electronic systems is limited by the reliability of the integrated
circuits. To guarantee the overall performance, the integrated circuit reliability must be …

SRAM stability analysis for different cache configurations due to bias temperature instability and hot carrier injection

T Liu, CC Chen, J Wu, L Milor - 2016 IEEE 34th International …, 2016 - ieeexplore.ieee.org
Bias Temperature Instability (BTI) and Hot Carrier Injections (HCI) are two of the main effects
that increase a transistor's threshold voltage and further cause performance degradations …

Remaining useful life prediction in embedded systems using an online auto-updated machine learning based modeling

O Djedidi, MA Djeziri, S Benmoussa - Microelectronics Reliability, 2021 - Elsevier
Abstract Systems on Chips are increasingly involved in critical equipment in the fields of
aeronautics, transportations, and energy. Therefore, monitoring their life cycle is a crucial …

A comprehensive time-dependent dielectric breakdown lifetime simulator for both traditional CMOS and FinFET technology

K Yang, T Liu, R Zhang, L Milor - IEEE Transactions on Very …, 2018 - ieeexplore.ieee.org
This paper presents techniques for gate-oxide and middle-of-line (MOL) time-dependent
dielectric breakdown (TDDB) lifetime assessment of microprocessors and digital circuits …

Comprehensive reliability-aware statistical timing analysis using a unified gate-delay model for microprocessors

T Liu, CC Chen, L Milor - IEEE Transactions on Emerging …, 2016 - ieeexplore.ieee.org
A framework is proposed to perform timing analysis of state-of-art microprocessors
considering the impact of process-voltage-temperature (PVT) variations and the aging effect …

Microprocessor aging analysis and reliability modeling due to back-end wearout mechanisms

CC Chen, L Milor - IEEE Transactions on Very Large Scale …, 2014 - ieeexplore.ieee.org
Back-end wearout mechanisms are major reliability concerns for modern microprocessors.
In this paper, a framework that contains modules for back-end time-dependent dielectric …

System-level variation-aware aging simulator using a unified novel gate-delay model for bias temperature instability, hot carrier injection, and gate oxide breakdown

T Liu, CC Chen, S Cha, L Milor - Microelectronics Reliability, 2015 - Elsevier
A framework is proposed to analyze system-level reliability and evaluate the lifetimes of
state-of-art microprocessors considering the impact of process–voltage–temperature (PVT) …

System-level modeling of microprocessor reliability degradation due to bias temperature instability and hot carrier injection

CC Chen, T Liu, L Milor - … on Very Large Scale Integration (VLSI …, 2016 - ieeexplore.ieee.org
Negative bias temperature instability (NBTI), positive bias temperature instability (PBTI), and
hot carrier injection (HCI) are leading reliability concerns for modern microprocessors. In this …

Comprehensive reliability and aging analysis on SRAMs within microprocessor systems

T Liu, CC Chen, W Kim, L Milor - Microelectronics Reliability, 2015 - Elsevier
A framework is proposed to analyze the impact of both Front End of the Line (FEOL) and
Back End of the Line (BEOL) wearout mechanisms on memories embedded within state-of …

Memory and logic lifetime simulation systems and methods

L Milor, T Liu, CC Chen - US Patent 10,514,973, 2019 - Google Patents
Aspects of the disclosed technology include a method including extracting, by a processor, a
plurality of features from one from among a layout of a circuit, a netlist of the circuit, and the …