Layout-aware selection of trace signals for post-silicon debug
P Thakyal, P Mishra - 2014 IEEE Computer Society Annual …, 2014 - ieeexplore.ieee.org
Post-silicon debug is widely acknowledged as a bottleneck in SoC design methodology. A
major challenge during post-silicon debug is the limited observability of internal signals …
major challenge during post-silicon debug is the limited observability of internal signals …
A Flexible Programmable Memory BIST Architecture
In the present paper a moderate area programmable memory built-in-self-test (BIST)
architecture supporting multiple algorithm loading is proposed. The entire BIST operation is …
architecture supporting multiple algorithm loading is proposed. The entire BIST operation is …
Layout-aware signal selection in reconfigurable architectures
P Thakyal, P Mishra - … Symposium on VLSI Design and Test, 2014 - ieeexplore.ieee.org
Post-silicon validation is an important and increasingly complex task in SoC design
methodology. One of the major challenges in post-silicon debug is the limited observability …
methodology. One of the major challenges in post-silicon debug is the limited observability …
Physical-Aware memory BIST datapath synthesis: Architecture and case-studies on complex SoCs
VR Devanathan, S Bhavsar… - 2011 Asian Test …, 2011 - ieeexplore.ieee.org
With increasing scaling, it is common to find large SoCs with more than 40M bits of
embedded SRAMs constituting more than 75% of total die area [1]. Physical design for such …
embedded SRAMs constituting more than 75% of total die area [1]. Physical design for such …
Reducing test power for embedded memories
With the increased number of embedded memories in mobile devices, minimizing the test
power becomes a serious concern, especially when parallel testing is applied. Battery will …
power becomes a serious concern, especially when parallel testing is applied. Battery will …
Computer security: the good, the bad and the ugly
C Meadows - Proceedings. IEEE High-Assurance Systems …, 1996 - ieeexplore.ieee.org
We discuss and characterize different types of solutions to computer security problems in
terms of bad (theoretically sound, but expensive and impractical), ugly (practical, but messy …
terms of bad (theoretically sound, but expensive and impractical), ugly (practical, but messy …
[PDF][PDF] LAYOUT-AWARE SIGNAL SELECTION FOR POST-SILICON DEBUG
P THAKYAL - 2014 - cise.ufl.edu
LAYOUT-AWARE SIGNAL SELECTION FOR POST-SILICON DEBUG By PRATEEK THAKYAL
A THESIS PRESENTED TO THE GRADUATE SCHOOL OF THE UNIVERS Page 1 …
A THESIS PRESENTED TO THE GRADUATE SCHOOL OF THE UNIVERS Page 1 …