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Optimizing energy consumption for data centers
Big data applications have become increasingly popular with the appearance of cloud
computing and green computing. Therefore, internet service providers (ISPs) need to build …
computing and green computing. Therefore, internet service providers (ISPs) need to build …
System-level power optimization: techniques and tools
This tutorial surveys design methods for energy-efficient system-level design. We consider
electronic sytems consisting of a hardware platform and software layers. We consider the …
electronic sytems consisting of a hardware platform and software layers. We consider the …
Reliability modeling of high-voltage power lines in a sharply continental climate
SR Khasanov, EI Gracheva… - E3S web of …, 2020 - e3s-conferences.org
One of the important elements of the high-voltage transmission line is 110 kV, the damage of
which leads to under-supply of electricity, ie reducing the reliability of the lines. Damage to …
which leads to under-supply of electricity, ie reducing the reliability of the lines. Damage to …
[КНИГА][B] Low-power electronics design
C Piguet - 2018 - books.google.com
The power consumption of integrated circuits is one of the most problematic considerations
affecting the design of high-performance chips and portable devices. The study of power …
affecting the design of high-performance chips and portable devices. The study of power …
[КНИГА][B] System-level design techniques for energy-efficient embedded systems
MT Schmitz, BM Al-Hashimi, P Eles - 2004 - books.google.com
System-Level Design Techniques for Energy-Efficient Embedded Systems addresses the
development and validation of co-synthesis techniques that allow an effective design of …
development and validation of co-synthesis techniques that allow an effective design of …
Dynamic hardware/software partitioning: A first approach
Partitioning an application among software running on a microprocessor and hardware co-
processors in on-chip configurable logic has been shown to improve performance and …
processors in on-chip configurable logic has been shown to improve performance and …
Low power system scheduling and synthesis
NK Jha - IEEE/ACM International Conference on Computer …, 2001 - ieeexplore.ieee.org
Many scheduling techniques have been presented recently which exploit dynamic voltage
scaling (DVS) and dynamic power management (DPM) for both uniprocessors, and …
scaling (DVS) and dynamic power management (DPM) for both uniprocessors, and …
[PDF][PDF] Modeling the Reliability of High-Voltage Power Transmission Lines Taking into Account the Influence of the Parameters of a Sharply Continental Climate.
E Gracheva, M Toshkhodzhaeva… - International Journal …, 2020 - researchgate.net
Natural factors significantly affect the reliability of overhead transmission lines (OHTLs) as
the operating conditions change with a change in natural conditions. As such, OHTLs in new …
the operating conditions change with a change in natural conditions. As such, OHTLs in new …
A study of the speedups and competitiveness of FPGA soft processor cores using dynamic hardware/software partitioning
Field programmable gate arrays (FPGAs) provide designers with the ability to create
hardware circuits quickly. Increases in FPGA configurable logic capacity and decreasing …
hardware circuits quickly. Increases in FPGA configurable logic capacity and decreasing …
Energy savings and speedups from partitioning critical software loops to hardware in embedded systems
We present results of extensive hardware/software partitioning experiments on numerous
benchmarks. We describe our loop-oriented partitioning methodology for moving critical …
benchmarks. We describe our loop-oriented partitioning methodology for moving critical …