Core-based system-on-chips (SoCs) fabricated on three-dimensional (3D) technology are
emerging for better integration capabilities. Effective test architecture design and …

A test solution for a complex system requires the design of a test access mechanism (TAM),
which is used for the test data transportation, and a test schedule of the test data …

Test planning for core-based system-on-a-chip (SOC) designs is necessary to reduce testing
time and test cost. In this paper we survey recent advances in test planning that address the …

Manufacturing test is a key step in the implementation flow of modern integrated electronic
products. It certifies the product quality, accelerates yield learning and influences the final …

Testing of Integrated Circuits is important to ensure the production of fault-free chips.
However, testing is becoming cumbersome and expensive due to the increasing complexity …

The cost of testing SOCs (systems-on-chip) is highly related to the test application time. The
problem is that the test application time increases as the technology makes it possible to …

In this paper, we propose an SOC (system-on-chip) test scheduling technique that minimizes
the test application time while considering test power limitations and test conflicts. The test …

During volume testing, test application time, test data volume and high performance
automatic test equipment (ATE) are the major cost factors. Embedded testing including built …

Multi-site testing is a popular and effective way to increase test throughput and reduce test
costs. We present a test throughput model, in which we focus on wafer testing, and consider …

In this paper, we propose a test pattern ordering algorithm for fault diagnosis. Test pattern
ordering is effective in situations where the fail log is truncated and contains a limited …