Addition is the key operation in digital systems, and floating-point adder (FPA) is frequently
used for real number addition because floating-point representation provides a large …

This seminal book presents a new logically determined design methodology for designing
clockless circuit systems. The book presents the foundations, architectures and …

Self-timed logic design methods are developed using Threshold Combinational Reduction
(TCR) within the NULL Convention Logic (NCL) paradigm. NCL logic functions are realized …

In this paper, a number of 4-bit, 8-operation arithmetic logic units (ALUs) are designed using
the delay-insensitive NULL convention logic paradigm, and are characterized in terms of …

This paper details the design of the fastest known asynchronous Multiply and Accumulate
unit (MAC) architecture published to date. The MAC architecture herein is based on the MAC …

The present work aims at proposing an efficient technique for signed binary multiplication
using unsigned, multiply instruction. Numerous examples are provided to show efficiency of …

The increasing power consumption in the synchronous circuits is the major concern in the
semiconductor industry. The major contributor to this power consumption is the clock …

For most of its history, computer architecture has been able to benefit from a rapid scaling in
semiconductor technology, resulting in continuous improvements to CPU design. During that …

Abstract Arithmetic and Logic Circuits are to be designed with less power, compact size, less
propagation delay in this fast growing era of technology. Arithmetic operations are …

Abstract An unsigned 8-bit÷ 4-bit delay-insensitive iterative divider is developed using the
NULL Convention Logic paradigm. the divider is simulated using a 0.5 μm CMOS process …