Computer architects employ a series of performance optimizations at the micro-architecture
level. These optimizations are meant to be invisible to the programmer but they are implicitly …

Leakage contracts have recently been proposed as a new security abstraction at the
Instruction Set Architecture (ISA) level. Leakage contracts aim to capture the information that …

Traditional modeling approaches in computer architecture aim to obtain an accurate
estimation of performance, area, and energy of a processor design. With the advent of …

Many SoCs employ system-level hardware access control mechanisms to ensure that
security-critical operations cannot be tampered with by less trusted components of the …

Modern out-of-order processors face speculative execution attacks. Despite various
proposed software and hardware mitigations to prevent such attacks, new attacks keep …

The importance of preventing microarchitectural timing side channels in security-critical
applications has surged immensely over the last several years. Constant-time programming …

To address transient execution vulnerabilities, processor architects have proposed both
defensive designs and formal descriptions of the security they provide. However, these …

Transient execution vulnerabilities have affected CPUs for the better part of the decade, yet,
we are still missing methods to efficiently uncover them at the design stage. Existing …

Formal verification is a critical task in hardware design today. Yet, while there has been
significant progress in improving technique automation and efficiency, scaling to large …

Protecting data in memory from attackers continues to be a concern in computing systems.
CHERI is a promising approach to achieve such protection, by providing and enforcing fine …