Oxide semiconductor heterojunction transistor with negative differential transconductance for multivalued logic circuits
Multivalued logic (MVL) technology is a promising solution for improving data density and
reducing power consumption in comparison to complementary metal-oxide-semiconductor …
reducing power consumption in comparison to complementary metal-oxide-semiconductor …
DC and RF/analog performances of split source horizontal pocket and hetero stack TFETs considering interface trap charges: a simulation study
This work investigates the impact of different types of interface trap charges (ITCs) on
electrical parameters of split source horizontal pocket Z shape TFET (ZHP-TFET) and Hetero …
electrical parameters of split source horizontal pocket Z shape TFET (ZHP-TFET) and Hetero …
Improvement in reliability of tunneling field-effect transistor with pnin structure
One of the major problems of pin tunneling field-effect transistor (TFET) is the reliability due
to the strong electric field near the tunneling junction. In this paper, using technology …
to the strong electric field near the tunneling junction. In this paper, using technology …
Investigating the effects of do** gradient, trap charges, and temperature on Ge vertical TFET for low power switching and analog applications
Influence of Gaussian do** in transistor regions, do** gradient step size (σ), interface
trap charges (ITC), and temperature on DC, Analog, and Linearity performance of Ge …
trap charges (ITC), and temperature on DC, Analog, and Linearity performance of Ge …
Interfacial trap charge and self-heating effect based reliability analysis of a Dual-Drain Vertical Tunnel FET
This manuscript exclusively addresses the reliability concern of a double-drain vertical TFET
(DD-VTFET) by analysing the influence of interface trap charges and variation in ambient …
(DD-VTFET) by analysing the influence of interface trap charges and variation in ambient …
Analysis on electrical parameters including temperature and interface trap charges in gate overlap Ge source step shape double gate TFET
In this paper, the electrical parameters are evaluated for the variations of temperature in
Gate Overlap Ge source Step Shape Double Gate TFET (GO-Ge-SSDG-TFET) under the …
Gate Overlap Ge source Step Shape Double Gate TFET (GO-Ge-SSDG-TFET) under the …
Temperature associated reliability issues of heterogeneous gate dielectric—gate all around—tunnel FET
In this paper, the temperature associated reliability issues of heterogeneous gate dielectric-
gate all around-tunnel FET (HD GAA TFET) has been addressed, and the results are …
gate all around-tunnel FET (HD GAA TFET) has been addressed, and the results are …
Noise behavior of vertical tunnel FETs under the influence of interface trap states
A detailed analysis of low frequency noise behavior of two different vertical TFETs namely
n+ pocket VTFET and dual MOS capacitor (D-MOS) VTFET is presented in this work …
n+ pocket VTFET and dual MOS capacitor (D-MOS) VTFET is presented in this work …
Impact of interface trap charges on electrical performance characteristics of a source pocket engineered Ge/Si heterojunction vertical TFET with HfO2/Al2O3 laterally …
This work reports the impact of interface trap charges (ITCs) on the electrical performance
characteristics of a source pocket engineered (SPE) Ge/Si heterojunction (HJ) vertical TFET …
characteristics of a source pocket engineered (SPE) Ge/Si heterojunction (HJ) vertical TFET …
Fin enabled area scaled tunnel FET
K Hemanjaneyulu, M Shrivastava - IEEE Transactions on …, 2015 - ieeexplore.ieee.org
While kee** the technological evolution and commercialization of FinFET technology in
mind, this paper discloses a novel concept that enables area-scaled or vertical tunneling in …
mind, this paper discloses a novel concept that enables area-scaled or vertical tunneling in …