On single-electron technology full adders

MH Sulieman, V Beiu - IEEE transactions on nanotechnology, 2005 - ieeexplore.ieee.org
This paper reviews several full adder (FA) designs in single-electron technology (SET). In
addition to the structure and size (ie, number of devices), this paper tries to provide a …

Majority-Logic, its applications, and atomic-scale embodiments

B Parhami, D Abedi, G Jaberipur - Computers & Electrical Engineering, 2020 - Elsevier
Today's computing is increasingly data-intensive, heralding the age of big data. With greater
data volumes, come the needs for faster processing, greater storage capacity, and …

Full-adder circuit design based on all-spin logic device

Q An, L Su, JO Klein, S Le Beux… - Proceedings of the …, 2015 - ieeexplore.ieee.org
Limiting or reducing the power consumption of the digital circuits for calculation is now the
main concern in nanoelectronic domain. For this purpose, spintronic devices are proposed …

A novel highly reliable low-power nano architecture when von Neumann augments Kolmogorov

V Beiu - Proceedings. 15th IEEE International Conference on …, 2004 - ieeexplore.ieee.org
This work presents a novel architecture, which is both device and circuit independent. The
starting idea is that computations can be performed in three fundamentally different ways …

On computing nano-architectures using unreliable nano-devices

V Beiu, W Ibrahim - Nano and Molecular Electronics Handbook, 2018 - taylorfrancis.com
This chapter will start with a brief review of nanoelectronic challenges while focusing on the
reliability challenge. One of the most recent call-to-arms [1] raises two fundamental …

Serial addition: Locally connected architectures

V Beiu, S Aunet, J Nyathi, RR Rydberg… - IEEE Transactions on …, 2007 - ieeexplore.ieee.org
This paper will briefly review nanoelectronic challenges while focusing on reliability. We
shall present and analyze a series of CMOS-based examples for addition starting from the …

Ultra low-power neural inspired addition: When serial might outperform parallel architectures

V Beiu, A Djupdal, S Aunet - … 8th International Work-Conference on Artificial …, 2005 - Springer
In this paper we analyse a serial (ripple carry) and a parallel (Kogge-Stone) adder when
operating in subthreshold at 100nm and 70nm. These are targeted for ultra low power …

Design and analysis of SET circuits: Using MATLAB modules and SIMON

M Sulieman, V Beiu - 4th IEEE Conference on Nanotechnology …, 2004 - ieeexplore.ieee.org
This paper describes two MATLAB modules which have been developed for enhancing
SIMON, a Monte Carlo simulator for single electron technology (SET) circuits. The first …

Object-oriented reliable distributed programming

O Hagsand, H Herzog, K Birman… - [1992] Proceedings of …, 1992 - ieeexplore.ieee.org
The importance of reliability in large distributed systems can not be underestimated.
Considerable effort has been directed towards the development of software reuse. However …

A fast, energy efficient, field programmable threshold-logic array

N Kulkarni, J Yang, S Vrudhula - … International Conference on …, 2014 - ieeexplore.ieee.org
Threshold-logic gates have long been known to result in more compact and faster circuits
when compared to conventional AND/OR logic equivalents [1], However, threshold logic …