Co-packaged photonics for high performance computing: status, challenges and opportunities

R Mahajan, X Li, J Fryman, Z Zhang… - Journal of Lightwave …, 2021 - ieeexplore.ieee.org
Photonics die or integrated photonics modules co-packaged with compute engines have the
potential to deliver significant improvements in power, bandwidth and reach needed to meet …

Photonic multiply-accumulate operations for neural networks

MA Nahmias, TF De Lima, AN Tait… - IEEE Journal of …, 2019 - ieeexplore.ieee.org
It has long been known that photonic communication can alleviate the data movement
bottlenecks that plague conventional microelectronic processors. More recently, there has …

CMOS inverter as analog circuit: An overview

W Bae - Journal of Low Power Electronics and Applications, 2019 - mdpi.com
Since the CMOS technology scaling has focused on improving digital circuit, the design of
conventional analog circuits has become more and more difficult. To overcome this …

Silicon photonic microring-based 4× 112 Gb/s WDM transmitter with photocurrent-based thermal control in 28-nm CMOS

J Sharma, Z Xuan, H Li, T Kim, R Kumar… - IEEE Journal of Solid …, 2021 - ieeexplore.ieee.org
This work presents a hybrid-integrated 4-micro-ring modulator-based wavelength-division
multiplexed (WDM) optical transmitter (OTX) in the O-band, suitable for co-packaged optics …

A 112-Gb/s—8.2-dBm Sensitivity 4-PAM Linear TIA in 16-nm CMOS With Co-Packaged Photodiodes

D Patel, A Sharif-Bakhtiar… - IEEE Journal of Solid …, 2022 - ieeexplore.ieee.org
A flip-chip co-packaged linear transimpedance amplifier (TIA) in 16-nm fin field effect
transistor (FinFET) CMOS demonstrating 112-Gb/s four-level pulse-amplitude modulation (4 …

A 100-Gb/s PAM-4 optical receiver with 2-tap FFE and 2-tap direct-feedback DFE in 28-nm CMOS

H Li, CM Hsu, J Sharma, J Jaussi… - IEEE Journal of Solid …, 2021 - ieeexplore.ieee.org
Optical receivers (ORXs) with integrated CMOS electronics enable compact, low-power
solutions for 400-G Ethernet and co-packaged optics. In this article, we present a 100-Gb/s …

A 112 Gb/s PAM4 Linear TIA with 0.96 pJ/bit Energy Efficiency in 28 nm CMOS

H Li, G Balamurugan, J Jaussi… - ESSCIRC 2018-IEEE …, 2018 - ieeexplore.ieee.org
This paper presents a 112 Gb/s PAM4 CMOS linear TIA to meet the requirements of
emerging 400G Ethernet standards for data center interconnect. A regulated inverter-based …

A 3D integrated energy-efficient transceiver realized by direct bond interconnect of co-designed 12 nm finfet and silicon photonic integrated circuits

PH Chang, A Samanta, P Yan, M Fu… - Journal of Lightwave …, 2023 - opg.optica.org
This article presents the first experimental demonstration of an energy-efficient electronic-
photonic co-designed transceiver circuit heterogeneously 3D co-integrated with high …

A Process and Temperature Insensitive CMOS Linear TIA for 100 Gb/s/ PAM-4 Optical Links

KR Lakshmikumar, A Kurylak… - IEEE Journal of Solid …, 2019 - ieeexplore.ieee.org
A linear transimpedance amplifier (TIA) for a 53 GBd PAM-4 optical link to support 100 Gb/s
data on a single wavelength is reported. Designed in a 16 nm FinFET CMOS process, the …

A 32 Gb/s, 4.7 pJ/bit optical link with− 11.7 dBm sensitivity in 14-nm FinFET CMOS

JE Proesel, Z Toprak-Deniz, A Cevrero… - IEEE Journal of Solid …, 2017 - ieeexplore.ieee.org
This paper presents a 32 Gb/s non-return-to-zero optical link using 850-nm vertical-cavity
surface-emitting laser-based multi-mode optics with 14-nm bulk FinFET CMOS circuits. The …