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A Survey of Design and Optimization for Systolic Array-based DNN Accelerators
In recent years, it has been witnessed that the systolic array is a successful architecture for
DNN hardware accelerators. However, the design of systolic arrays also encountered many …
DNN hardware accelerators. However, the design of systolic arrays also encountered many …
Fact: Ffn-attention co-optimized transformer architecture with eager correlation prediction
Transformer model is becoming prevalent in various AI applications with its outstanding
performance. However, the high cost of computation and memory footprint make its …
performance. However, the high cost of computation and memory footprint make its …
Highlight: Efficient and flexible dnn acceleration with hierarchical structured sparsity
Due to complex interactions among various deep neural network (DNN) optimization
techniques, modern DNNs can have weights and activations that are dense or sparse with …
techniques, modern DNNs can have weights and activations that are dense or sparse with …
Reconfigurability, why it matters in ai tasks processing: A survey of reconfigurable ai chips
Nowadays, artificial intelligence (AI) technologies, especially deep neural networks (DNNs),
play an vital role in solving many problems in both academia and industry. In order to …
play an vital role in solving many problems in both academia and industry. In order to …
ELSA: Exploiting layer-wise n: m sparsity for vision transformer acceleration
N: M sparsity is an emerging model compression method supported by more and more
accelerators to speed up sparse matrix multiplication in deep neural networks. Most existing …
accelerators to speed up sparse matrix multiplication in deep neural networks. Most existing …
Vegeta: Vertically-integrated extensions for sparse/dense gemm tile acceleration on cpus
Deep Learning (DL) acceleration support in CPUs has recently gained a lot of traction, with
several companies (Arm, Intel, IBM) announcing products with specialized matrix engines …
several companies (Arm, Intel, IBM) announcing products with specialized matrix engines …
RM-STC: Row-Merge Dataflow Inspired GPU Sparse Tensor Core for Energy-Efficient Sparse Acceleration
This paper proposes RM-STC, a novel GPU tensor core architecture designed for sparse
Deep Neural Networks (DNNs) with two key innovations:(1) native support for both training …
Deep Neural Networks (DNNs) with two key innovations:(1) native support for both training …
Automated HW/SW co-design for edge AI: State, challenges and steps ahead
Gigantic rates of data production in the era of Big Data, Internet of Thing (IoT), and Smart
Cyber Physical Systems (CPS) pose incessantly escalating demands for massive data …
Cyber Physical Systems (CPS) pose incessantly escalating demands for massive data …
PDP: parameter-free differentiable pruning is all you need
DNN pruning is a popular way to reduce the size of a model, improve the inferencelatency,
and minimize the power consumption on DNN accelerators. However, existing approaches …
and minimize the power consumption on DNN accelerators. However, existing approaches …
ETTE: Efficient tensor-train-based computing engine for deep neural networks
Tensor-train (TT) decomposition enables ultra-high compression ratio, making the deep
neural network (DNN) accelerators based on this method very attractive. TIE, the state-of-the …
neural network (DNN) accelerators based on this method very attractive. TIE, the state-of-the …