A new circuit-level technique for leakage and short-circuit power reduction of static logic gates in 22-nm CMOS technology
The leakage power, aka static power, increases in deep-submicron technologies due to
short-channel effects. This article proposes a novel input-controlled leakage restrainer …
short-channel effects. This article proposes a novel input-controlled leakage restrainer …
Always-on, sub-300-nw, event-driven spiking neural network based on spike-driven clock-generation and clock-and power-gating for an ultra-low-power intelligent …
Always-on artificial intelligent (AI) functions such as keyword spotting (KWS) and visual
wake-up tend to dominate total power consumption in ultra-low power devices [1]. A key …
wake-up tend to dominate total power consumption in ultra-low power devices [1]. A key …
An 88-fJ/40-MHz [0.4 V]–0.61-pJ/1-GHz [0.9 V] Dual-Mode Logic 8 8 bit Multiplier Accumulator With a Self-Adjustment Mechanism in 28-nm FD-SOI
The unique ability of dual-mode logic (DML) to self-adapt to computational needs by
providing high speed and/or low energy consumption is demonstrated for the first time by …
providing high speed and/or low energy consumption is demonstrated for the first time by …
A 0.8-V, 1.54-pJ/940-MHz dual-mode logic-based 16× 16-b booth multiplier in 16-nm FinFET
The dual-mode logic (DML) defines runtime adapted digital architectures that switch to either
improved performance or lower energy consumption as a function of the actual …
improved performance or lower energy consumption as a function of the actual …
Catena: A near-threshold, sub-0.4-mW, 16-core programmable spatial array accelerator for the ultralow-power mobile and embedded Internet of Things
In this article, we present Catena, a near-threshold voltage 16-core programmable spatial
array accelerator supporting workloads for ultralow-power (ULP) mobile and embedded …
array accelerator supporting workloads for ultralow-power (ULP) mobile and embedded …
[KSIĄŻKA][B] Dual Mode Logic: A New Paradigm for Digital IC Design
Dual Mode Logic: A New Paradigm for Digital IC Design | SpringerLink Skip to main content
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Always-on sub-microwatt spiking neural network based on spike-driven clock-and power-gating for an ultra-low-power intelligent device
This paper presents a novel spiking neural network (SNN) classifier architecture for enabling
always-on artificial intelligent (AI) functions, such as keyword spotting (KWS) and visual …
always-on artificial intelligent (AI) functions, such as keyword spotting (KWS) and visual …
A fW-and kHz-class feedforward leakage self-suppression logic requiring no external sleep signal to enter the leakage suppression mode
In this letter, we present a novel logic family for nanowatt and subnanowatt always-on
circuits. This logic family achieves the ultralow leakage of 5 fW per gate without requiring …
circuits. This logic family achieves the ultralow leakage of 5 fW per gate without requiring …
Snake: An asynchronous pipeline for ultra-low-power applications
Z Zhu, Y Yu, X Bai, S Qiao, Y Hei - IEICE Electronics Express, 2019 - jstage.jst.go.jp
Voltage scaling is an effective technique for ultra-low-power applications. However, PVT
variation degrades the robust of traditional synchronous pipelines severely when voltage …
variation degrades the robust of traditional synchronous pipelines severely when voltage …
A New Circuit‑Level Leakage Power Reduction Technique of Static Logic Gates for Analog to Digital Converter in CMOS Technology using Virtuoso
The total power in a device is composed of three basic components, having dynamic power
due to switching activity, static power while the device in sleep mode and short circuit power …
due to switching activity, static power while the device in sleep mode and short circuit power …