Exploring neuromorphic computing based on spiking neural networks: Algorithms to hardware

N Rathi, I Chakraborty, A Kosta, A Sengupta… - ACM Computing …, 2023 - dl.acm.org
Neuromorphic Computing, a concept pioneered in the late 1980s, is receiving a lot of
attention lately due to its promise of reducing the computational energy, latency, as well as …

PUMA: A programmable ultra-efficient memristor-based accelerator for machine learning inference

A Ankit, IE Hajj, SR Chalamalasetti, G Ndu… - Proceedings of the …, 2019 - dl.acm.org
Memristor crossbars are circuits capable of performing analog matrix-vector multiplications,
overcoming the fundamental energy efficiency limitations of digital logic. They have been …

Neural network accelerator design with resistive crossbars: Opportunities and challenges

S Jain, A Ankit, I Chakraborty, T Gokmen… - IBM Journal of …, 2019 - ieeexplore.ieee.org
Deep neural networks (DNNs) achieve best-known accuracies in many machine learning
tasks involved in image, voice, and natural language processing and are being used in an …

Compute-in-memory technologies and architectures for deep learning workloads

M Ali, S Roy, U Saxena, T Sharma… - … Transactions on Very …, 2022 - ieeexplore.ieee.org
The use of deep learning (DL) to real-world applications, such as computer vision, speech
recognition, and robotics, has become ubiquitous. This can be largely attributed to a virtuous …

Magnetoresistive circuits and systems: Embedded non-volatile memory to crossbar arrays

A Agrawal, C Wang, T Sharma… - IEEE Transactions on …, 2021 - ieeexplore.ieee.org
This overview article describes Magnetoresistive Random Access Memory (MRAM) from a
circuits and systems perspective. We discuss various tradeoffs and design challenges of …

SPARE: Spiking neural network acceleration using ROM-embedded RAMs as in-memory-computation primitives

A Agrawal, A Ankit, K Roy - IEEE Transactions on Computers, 2018 - ieeexplore.ieee.org
From the little we know about the human brain, the inherent cognitive mechanism is very
different from the de facto state-of-the-art computing platforms. The human brain uses …

R-mram: A rom-embedded stt mram cache

D Lee, X Fong, K Roy - IEEE electron device letters, 2013 - ieeexplore.ieee.org
We present a new spin-transfer torque magnetic random access memory (STT MRAM) bit-
cell that is embedded with read-only memory (ROM) functionality. The proposed ROM …

Design of low power SRAM on Artix-7 FPGA

T Agrawal, A Kumar… - 2016 2nd International …, 2016 - ieeexplore.ieee.org
SRAM is associated with cache memory inside computer system, it increases overall speed
of the system. In this work 64kb SRAM is synthesized and simulated on Artix-7 FPGA board …

Embedding read-only memory in spin-transfer torque MRAM-based on-chip caches

X Fong, R Venkatesan, D Lee… - … Transactions on Very …, 2015 - ieeexplore.ieee.org
We propose a design technique for embedding read-only memory (ROM) in spin-transfer
torque MRAM (STT-MRAM) arrays by adding an extra bit-line in every column of the array …

Fault tolerant reconfigurable hardware design using BIST on SRAM: A review

AKS Pundir, OP Sharma - 2017 International Conference on …, 2017 - ieeexplore.ieee.org
This Paper presents an exhaustive review on BIST technique used in different fault tolerant
systems and also consider the fault detection methodologies used in these systems. BIST is …