[PDF][PDF] Design and implementation of DA FIR filter for bio-inspired computing architecture
This paper elucidates the system construct of DA-FIR filter optimized for design of distributed
arithmetic (DA) finite impulse response (FIR) filter and is based on architecture with tightly …
arithmetic (DA) finite impulse response (FIR) filter and is based on architecture with tightly …
Designing a D-Flipflop Using Novel Sleep Transistor Technique
CM Reddy, S Dhara, B Srikanth… - 2022 IEEE …, 2022 - ieeexplore.ieee.org
D-Flipflops are widely used in designing various analogue, digital and mixed signals.
Different shift registers, counters and other circuits are designed using D-Flipflop. To …
Different shift registers, counters and other circuits are designed using D-Flipflop. To …
Image-Based Authentication Security Improvement by Randomized Selection Approach
In recent days, the value of data stored in disk space (may be localized or cloud) is on the
higher side while comparing to the past. In these circumstances, higher the information …
higher side while comparing to the past. In these circumstances, higher the information …
Energy-Efficient D-Flipflop Circuit using Novel Sleep Transistor in 45nm Technology Node
A Rathore, N Sood - 2024 2nd International Conference on …, 2024 - ieeexplore.ieee.org
Many analog, digital, and mixed signals are designed using D-Flipflops. The voltage applied
to the circuit during sleep operation must be lowered to prolong battery life and lower power …
to the circuit during sleep operation must be lowered to prolong battery life and lower power …
Performance and Analysis of Approximate Multipliers using Modified Dual-Stage 5: 2 Compressors
B Srikanth, AS Jahnavi, S Tiwari… - 2023 4th International …, 2024 - ieeexplore.ieee.org
This paper presents a modified approach to approximate multiplier design utilizing dual-
stage 5: 2 compressors. Multipliers are fundamental components in digital signal processing …
stage 5: 2 compressors. Multipliers are fundamental components in digital signal processing …
Design and Implementation of Low Power Golay Encoder Architecture
B Srikanth, DS Pranathi, PSK Raju… - 2024 5th International …, 2024 - ieeexplore.ieee.org
In wireless communication, the transmission of a message from source to destination may
be susceptible to distortion or corruption due to noise. Error detection involves identifying …
be susceptible to distortion or corruption due to noise. Error detection involves identifying …
[PDF][PDF] An efficient debugging architecture for DTG based FIR filter using I2C protocol in DSP processor
Nowadays, the debugging process in the Field Programmable Gate Array (FPGA) platform is
more essential to manufacture the hardware device without error. Normally, the Digital …
more essential to manufacture the hardware device without error. Normally, the Digital …
[PDF][PDF] Reset logic verification of an iod at system on chip level using gatesim
KL Maidhili, F Noorbasha, A Vamsi… - International …, 2020 - academia.edu
These days SOC became very essential part and it is a great revolution in electronics world.
Basically, for any SOC or (IP) verification results are very important as we cannot predict that …
Basically, for any SOC or (IP) verification results are very important as we cannot predict that …
[CITATION][C] An application on women safety using embedded systems and IoT
KH Kishore - Turkish Journal of Computer and Mathematics …, 2021
[CITATION][C] FPGA implementation of proficient 16-Tap FIR filter design using decision tree algorithm
A Murali - Turkish Journal of Computer and Mathematics …, 2021