Area–time–energy efficient architecture of CBNS‐based fast Fourier transform

K Das, E Harshavardhan Reddy… - … Journal of Circuit …, 2024 - Wiley Online Library
A new approach for implementing the fast Fourier transform (FFT) using complex binary
number system (CBNS) is presented in this paper. The advantage of using CBNS is that …

An efficient Radix-4 butterfly structure based on the complex binary number system and distributed arithmetic.

K Bowlyn, S Hounsinou… - International Journal of …, 2025 - search.ebscohost.com
Complex number arithmetic is pivotal in various applications, requiring the selection of an
efficient multiplier for high-performance computations. Fast Fourier transform (FFT)-based …

2-D Systolic Array architecture of CBNS based discrete Hilbert transform processor

M Mukherjee, SK Sanyal - Microprocessors and Microsystems, 2021 - Elsevier
This paper proposes an optimized design of Discrete Hilbert Transform (DHT) processor
using Complex Binary Number System (CBNS). The conventional implementation of DHT …

[PDF][PDF] Complex binary adder designs and their hardware implementations

T Jamil, M Awadalla, I Mohammed - International Journal of …, 2019 - researchgate.net
Complex Binary Number System (CBNS) is (-1+ j)-based on binary number system which
facilitates both real and imaginary components of a complex number to be represented as …

Design of CBNS nibble size adder using pass transistor logic circuit: extension to FPGA implementation

M Mukherjee, SK Sanyal - 2017 8th International Conference …, 2017 - ieeexplore.ieee.org
This paper focuses on the design of CBNS Nibble Size adder for fast signal processing. A
modular based approach has been undertaken both for Pass Transistor as well as Gate …

Complex binary associative dataflow processor-a tutorial

T Jamil - SoutheastCon 2018, 2018 - ieeexplore.ieee.org
Complex numbers play an important role in engineering applications such as digital signal
processing and image processing. To represent these numbers in binary, a “divide-and …

Design of high speed modified full adder

M Wari, D Shamuganandam, D Arumugan… - AIP Conference …, 2024 - pubs.aip.org
For carry-generation process, modern 4 bit carry look-ahead (CLA) designs is suggested.
Instead of using the carry functions for creation and dissemination that remain commonly …

Method for diagnosing data errors of a computer system functioning in the system of residual classes

S Koshman, V Krasnobayev… - Advanced Information …, 2021 - ais.khpi.edu.ua
{ } { } Page 1 Advanced Information Systems. 2021. Vol. 5, No. 3 ISSN 2522-9052 76 UDC
681.142 doi: https://doi.org/10.20998/2522-9052.2021.3.10 Serhii Koshman1, Victor …

[PDF][PDF] Complex Binary Subtractor Designs and their Hardware Implementations

T Jamil, M Awadalla, I Mohammed - International Journal of …, 2021 - academia.edu
ABSTRACT Complex Binary Number System (CBNS) is (-1+ j)-based binary number system
which facilitates both real and imaginary components of a complex number to be …

Design of a high-speed reconfigurable fast hartley transform processor using CBNS

M Mukherjee, SK Sanyal - 2017 14th IEEE India Council …, 2017 - ieeexplore.ieee.org
This paper proposes a high speed Fast Hartley Transform (FHT) processor using Complex
Binary Number System (CBNS). The proposed FHT architecture with the properties of …